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path: root/opcodes/aarch64-tbl.h
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2020-11-16aarch64: Extract Condition flag manipulation feature from Armv8.4-APrzemyslaw Wirkus1-4/+9
2020-11-11aarch64: Allow LS64 feature with Armv8.6Przemyslaw Wirkus1-1/+1
2020-11-09aarch64: Limit Rt register number for LS64 load/store instructionsPrzemyslaw Wirkus1-4/+5
2020-11-06aarch64: Extract Pointer Authentication feature from Armv8.3-APrzemyslaw Wirkus1-33/+38
2020-11-03[PATCH][GAS] aarch64: Add atomic 64-byte load/store instructions for Armv8.7Przemyslaw Wirkus1-2/+16
2020-10-30[PATCH][GAS] aarch64: Add WFIT instruction for Armv8.7-aPrzemyslaw Wirkus1-0/+1
2020-10-28aarch64: Add CSR PDEC instructionPrzemyslaw Wirkus1-0/+8
2020-10-28aarch64: Add WFET instruction for Armv8.7-aPrzemyslaw Wirkus1-0/+1
2020-10-28aarch64: Add DSB instruction Armv8.7-a variantPrzemyslaw Wirkus1-0/+5
2020-10-28aarch64: Add basic support for armv8.7-a architecturePrzemyslaw Wirkus1-0/+3
2020-09-08aarch64: Add support for Armv8-R DFB aliasAlex Coplan1-0/+6
2020-04-30AArch64: add GAS support for UDF instructionAlex Coplan1-0/+3
2020-04-20[AArch64, Binutils] Add missing TSB instructionSudakshina Das1-2/+3
2020-04-20[AArch64, Binutils] Make hint space instructions valid for Armv8-aSudakshina Das1-30/+17
2020-01-31aarch64: Fix MOVPRFX markup for bf16 conversionsRichard Sandiford1-2/+2
2020-01-27AArch64: Fix cfinv disassembly issuesTamar Christina1-1/+8
2020-01-03Arm64: correct address index operands for LD1RO{H,W,D}Jan Beulich1-4/+4
2020-01-03Arm64: correct {su,us}dot SIMD encodingsJan Beulich1-3/+3
2020-01-03Arm64: correct uzp{1,2} mnemonicsJan Beulich1-2/+2
2020-01-03Arm64: correct 64-bit element fmmla encodingJan Beulich1-1/+1
2020-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2019-12-05Arm64: simplify Crypto arch extension handlingJan Beulich1-12/+0
2019-11-11Arm64: SVE2's smaxp/sminp require operands 1 and 3 to be the same registerJan Beulich1-2/+2
2019-11-07[gas][aarch64] Add the v8.6 Data Gathering Hint mnemonic [10/X]Matthew Malcomson1-0/+5
2019-11-07[binutils][aarch64] Matrix Multiply extension enablement [8/X]Matthew Malcomson1-0/+74
2019-11-07[binutils][aarch64] Bfloat16 enablement [2/X]Matthew Malcomson1-0/+80
2019-11-07[gas][aarch64] Armv8.6-a option [1/X]Matthew Malcomson1-0/+3
2019-10-30Modify the ARNM assembler to accept the omission of the immediate argument fo...Delia Burduv1-1/+1
2019-07-02[AArch64] Allow MOVPRFX to be used with FMOVRichard Sandiford1-1/+1
2019-07-02[AArch64] Add missing C_MAX_ELEM flags for SVE conversionsRichard Sandiford1-28/+28
2019-07-01[gas][aarch64][SVE2] Fix pmull{t,b} requirement on SVE2-AESMatthew Malcomson1-5/+10
2019-05-09[binutils][aarch64] Add SVE2 instructions.Matthew Malcomson1-0/+419
2019-05-09[binutils][aarch64] New SVE_SHLIMM_UNPRED_22 operand.Matthew Malcomson1-0/+3
2019-05-09[binutils][aarch64] New SVE_Zm4_11_INDEX operand.Matthew Malcomson1-0/+3
2019-05-09[binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand.Matthew Malcomson1-2/+5
2019-05-09[binutils][aarch64] New SVE_ADDR_ZX operand.Matthew Malcomson1-0/+3
2019-05-09[binutils][aarch64] New SVE_Zm3_11_INDEX operand.Matthew Malcomson1-0/+3
2019-05-09[binutils][aarch64] Introduce SVE_IMM_ROT3 operand.Matthew Malcomson1-0/+2
2019-05-09[binutils][aarch64] SVE2 feature extension flags.Matthew Malcomson1-0/+36
2019-05-01[BINUTILS, AArch64] Enable Transactional Memory ExtensionSudakshina Das1-0/+18
2019-04-11[BINUTILS, AArch64, 2/2] Update Store Allocation Tag instructionsSudakshina Das1-9/+12
2019-04-11[BINUTILS, AArch64, 1/2] Add new LDGM/STGM instructionSudakshina Das1-0/+2
2019-02-07AArch64: Add verifier for By elem Single and Double sized instructions.Tamar Christina1-8/+10
2019-01-25AArch64: Update encodings for stg, st2g, stzg and st2zg.Sudi Das1-10/+10
2019-01-25AArch64: Add new STZGM instruction for Armv8.5-A Memory Tagging Extension.Sudi Das1-0/+1
2019-01-25AArch64: Remove ldgv and stgv instructions from Armv8.5-A Memory Tagging Exte...Sudi Das1-4/+0
2019-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2018-12-03[aarch64] - Only use MOV for disassembly when shifter op is LSL #0Egeyar Bagcioglu1-1/+1
2018-11-12[BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging ExtensionSudakshina Das1-0/+4
2018-11-12[BINUTILS, AARCH64, 5/8] Add Tag getting instruction in Memory Tagging ExtensionSudakshina Das1-0/+7