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path: root/opcodes/aarch64-tbl.h
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2016-03-18Fix the disassembly of the AArch64's OOR instruction as a MOV instruction.Nick Clifton1-1/+1
2016-01-01Copyright update for binutilsAlan Modra1-1/+1
2015-12-14[AArch64][PATCH 14/14] Support FP16 Adv.SIMD Scalar Shift By Immediate instru...Matthew Wahab1-0/+14
2015-12-14[AArch64][PATCH 13/14] Support FP16 Adv.SIMD Shift By Immediate instructions.Matthew Wahab1-0/+15
2015-12-14[AArch64][PATCH 12/14] Support FP16 Adv.SIMD Scalar Pairwise instructions.Matthew Wahab1-0/+16
2015-12-14[AArch64][PATCH 9/14] Support FP16 Adv.SIMD Modified Immediate instructions.Matthew Wahab1-0/+9
2015-12-14[AArch64][PATCH 8/14] Support FP16 Adv.SIMD Across Lanes instructions.Matthew Wahab1-0/+15
2015-12-14[AArch64][PATCH 7/14] Support FP16 Scalar Indexed Element instructions.Matthew Wahab1-0/+8
2015-12-14[AArch64][PATCH 6/14] Support FP16 Vector Indexed Element instructions.Matthew Wahab1-0/+15
2015-12-14[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.Matthew Wahab1-0/+52
2015-12-14[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.Matthew Wahab1-0/+65
2015-12-14[AArch64][PATCH 3/14] Support ARMv8.2 FP16 Scalar Three Same instructions.Matthew Wahab1-0/+18
2015-12-14[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.Matthew Wahab1-0/+55
2015-12-14[AArch64][PATCH 1/14] Support ARMv8.2 FP16 Adv.SIMD instructions.Matthew Wahab1-0/+3
2015-12-11[AArch64][Patch 5/5] Add instruction PSB CSYNCMatthew Wahab1-1/+8
2015-12-11[AArch64][Patch 4/5] Support HINT aliases taking operands.Matthew Wahab1-2/+2
2015-12-10[AArch64][PATCH 1/2] Add support for RAS instruction ESB.Matthew Wahab1-0/+4
2015-11-27[AArch64][PATCH 3/3] Add floating-point FP16 instructionsMatthew Wahab1-0/+164
2015-11-27[AArch64][PATCH 1/3] Support ARMv8.2 FP16 floating point instructions.Matthew Wahab1-0/+3
2015-11-27[AArch64] Add ARMv8.2 instruction alias REV64.Matthew Wahab1-1/+4
2015-11-27[AArch64] Add ARMv8.2 instructions BFC and REV64.Matthew Wahab1-0/+12
2015-08-11Fix the disassembly of the AArch64 SIMD EXT instruction.Nick Clifton1-1/+1
2015-06-02[AArch64] Support for ARMv8.1a Adv.SIMD instructionsMatthew Wahab1-0/+13
2015-06-02[AArch64] Support for ARMv8.1a Limited Ordering Regions extensionMatthew Wahab1-0/+10
2015-03-10[AARCH64] Remove Load/Store register (unscaled immediate) alias.Jiong Wang1-24/+12
2015-01-02ChangeLog rotatation and copyright year updateAlan Modra1-1/+1
2014-09-03[PATCH/AArch64] Generic support for all system registers using mrs and msrJiong Wang1-2/+2
2014-09-03[PATCH/AArch64] Implement LSE featureJiong Wang1-3/+188
2014-03-05Update copyright yearsAlan Modra1-1/+1
2014-02-27opcodes/Yufeng Zhang1-10/+10
2013-11-05gas/Yufeng Zhang1-6/+8
2013-02-28include/opcode/Yufeng Zhang1-0/+24
2013-01-30include/opcode/Yufeng Zhang1-4/+8
2013-01-17include/opcode/Yufeng Zhang1-4/+4
2013-01-04opcodes/Yufeng Zhang1-4/+4
2012-08-13Add support for 64-bit ARM architecture: AArch64Nick Clifton1-0/+2253
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