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path: root/opcodes/aarch64-opc.c
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2020-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2019-12-17ubsan: aarch64: left shift cannot be represented in type 'int64_t'Alan Modra1-12/+11
2019-11-11Arm64: fix build with old glibcJan Beulich1-10/+7
2019-11-07[binutils][aarch64] Matrix Multiply extension enablement [8/X]Matthew Malcomson1-0/+2
2019-11-07[binutils][aarch64] Bfloat16 enablement [2/X]Matthew Malcomson1-0/+1
2019-10-30Modify the ARNM assembler to accept the omission of the immediate argument fo...Delia Burduv1-1/+6
2019-08-22[AArch64][gas] Update MTE system register encodingsKyrylo Tkachov1-10/+10
2019-07-23[AArch64] Add support for GMID_EL1 register for +memtagKyrylo Tkachov1-1/+3
2019-07-02[AArch64] Fix bogus MOVPRFX warning for GPR form of CPYRichard Sandiford1-5/+0
2019-05-09[binutils][aarch64] New SVE_SHLIMM_UNPRED_22 operand.Matthew Malcomson1-0/+2
2019-05-09[binutils][aarch64] New SVE_Zm4_11_INDEX operand.Matthew Malcomson1-0/+3
2019-05-09[binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand.Matthew Malcomson1-6/+12
2019-05-09[binutils][aarch64] New sve_size_sd2 iclass.Matthew Malcomson1-0/+1
2019-05-09[binutils][aarch64] New SVE_ADDR_ZX operand.Matthew Malcomson1-0/+18
2019-05-09[binutils][aarch64] New SVE_Zm3_11_INDEX operand.Matthew Malcomson1-0/+4
2019-05-09[binutils][aarch64] New iclass sve_size_hsd2.Matthew Malcomson1-0/+1
2019-05-09[binutils][aarch64] Introduce SVE_IMM_ROT3 operand.Matthew Malcomson1-0/+3
2019-05-09[binutils][aarch64] Allow movprfx for SVE2 instructions.Matthew Malcomson1-1/+3
2019-05-01[BINUTILS, AArch64] Enable Transactional Memory ExtensionSudakshina Das1-0/+2
2019-04-11[BINUTILS, AArch64, 2/2] Update Store Allocation Tag instructionsSudakshina Das1-0/+2
2019-02-07AArch64: Add verifier for By elem Single and Double sized instructions.Tamar Christina1-0/+24
2019-01-25AArch64: Remove ldgv and stgv instructions from Armv8.5-A Memory Tagging Exte...Sudi Das1-6/+0
2019-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2018-12-18Include bfd_stdint.h in bfd.hAlan Modra1-1/+1
2018-11-12[BINUTILS, AARCH64, 8/8] Add data cache instructions for Memory Tagging Exten...Sudakshina Das1-0/+40
2018-11-12[BINUTILS, AARCH64, 7/8] Add system registers for Memory Tagging ExtensionSudakshina Das1-0/+26
2018-11-12[BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging ExtensionSudakshina Das1-0/+6
2018-11-12[BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging Exten...Sudakshina Das1-0/+35
2018-11-12[BINUTILS, AARCH64, 2/8] Add Tag generation instructions in Memory Tagging Ex...Sudakshina Das1-0/+19
2018-10-16AArch64: Fix error checking for SIMD udot (by element)Matthew Malcomson1-1/+2
2018-10-09[PATCH, BINUTULS, AARCH64, 9/9] Add SSBS to MSR/MRSSudakshina Das1-0/+14
2018-10-09[PATCH, BINUTILS, AARCH64, 8/9] Add SCXTNUM_ELx and ID_PFR2_EL1 system registersSudakshina Das1-0/+20
2018-10-09[PATCH, BINUTILS, AARCH64, 7/9] Add BTI instructionSudakshina Das1-3/+10
2018-10-09[PATCH, BINUTILS, AARCH64, 6/9] Add Random number instructionsSudakshina Das1-0/+10
2018-10-09[PATCH, BINUTILS, AARCH64, 5/9] Add DC CVADP instructionSudakshina Das1-0/+6
2018-10-09[PATCH, BINUTILS, AARCH64, 4/9] Add Execution and Data Restriction instructionsSudakshina Das1-0/+17
2018-10-08AArch64: Replace C initializers with memsetTamar Christina1-1/+3
2018-10-03AArch64: Constraint disassembler and assembler changes.Tamar Christina1-3/+3
2018-10-03AArch64: Add SVE constraints verifier.Tamar Christina1-1/+348
2018-10-03AArch64: Refactor verifiers to make more general.Tamar Christina1-6/+9
2018-07-06Fix the read/write flag for these registers on AArch64Tamar Christina1-5/+5
2018-06-29Fix AArch64 encodings for by element instructions.Tamar Christina1-1/+2
2018-05-15Implement Read/Write constraints on system registers on AArch64Tamar Christina1-90/+99
2018-05-15Allow non-fatal errors to be emitted and for disassembly notes be placed on A...Tamar Christina1-1/+1
2018-05-15Modify AArch64 Assembly and disassembly functions to be able to fail and repo...Tamar Christina1-2/+2
2018-03-28Enhance the AARCH64 assembler to support LDFF1xx instructions which use REG+R...Nick Clifton1-0/+2
2018-01-03Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2017-12-19Correct disassembly of dot product instructions.Tamar Christina1-0/+1
2017-12-19Add support for V_4B so we can properly reject it.Tamar Christina1-0/+1
2017-11-09Add assembler and disassembler support for the new Armv8.4-a registers for AA...Tamar Christina1-1/+147