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path: root/opcodes/aarch64-opc.c
AgeCommit message (Expand)AuthorFilesLines
2024-03-18aarch64: Add support for (M)ADDPT and (M)SUBPT instructionsYury Khrustalev1-0/+25
2024-01-24aarch64: Eliminate unused variable warnings with -DNDEBUGAndrew Carlotti1-5/+4
2024-01-15aarch64: rcpc3: add support in general_constraint_met_pVictor Do Nascimento1-0/+40
2024-01-15aarch64: rcpc3: New RCPC3_ADDR operand typesVictor Do Nascimento1-0/+5
2024-01-15aarch64: rcpc3: Define address operand fields and inserter/extractorsVictor Do Nascimento1-0/+2
2024-01-15aarch64: rcpc3: Create implicit load/store size calc functionVictor Do Nascimento1-0/+22
2024-01-15aarch64: Fix tlbi and tlbip instructionsAndrew Carlotti1-141/+92
2024-01-15aarch64: Refactor aarch64_sys_ins_reg_supported_pAndrew Carlotti1-377/+204
2024-01-15aarch64: Add SVE2.1 Contiguous load/store instructions.Srinath Parvathaneni1-1/+10
2024-01-15aarch64: Add SVE2.1 dupq, eorqv and extq instructions.Srinath Parvathaneni1-0/+14
2024-01-15aarch64: Add support for FEAT_SME2p1 instructions.Srinath Parvathaneni1-0/+77
2024-01-12aarch64: Add +xs flag for existing instructionsAndrew Carlotti1-1/+1
2024-01-09aarch64: Add support for 128-bit system register mrrs and msrr insnsVictor Do Nascimento1-1/+8
2024-01-09aarch64: Add xs variants of tlbip operandsVictor Do Nascimento1-0/+124
2024-01-09aarch64: Add support for the SYSP 128-bit system instructionVictor Do Nascimento1-1/+1
2024-01-09aarch64: Add support for xzr register in register pair operandsVictor Do Nascimento1-2/+17
2024-01-04Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2023-11-16aarch64: Add new AT system instructions.Srinath Parvathaneni1-0/+9
2023-11-16aarch64: Add SLC target for PRFM instruction.Srinath Parvathaneni1-6/+6
2023-11-09aarch64: Fix error in THE system register checkingVictor Do Nascimento1-1/+1
2023-11-07aarch64: Add LSE128 instruction operand supportVictor Do Nascimento1-0/+4
2023-11-07aarch64: Add THE system register supportVictor Do Nascimento1-0/+5
2023-11-02aarch64: Add support for GCSB DSYNC instruction.Srinath Parvathaneni1-0/+5
2023-11-02aarch64: Add support for Check Feature Status Extension.Srinath Parvathaneni1-0/+4
2023-10-04aarch64: Refactor system register dataVictor Do Nascimento1-1068/+20
2023-10-04aarch64: system register aliasing detectionVictor Do Nascimento1-1/+8
2023-09-26aarch64: Restructure feature flag handlingRichard Sandiford1-29/+25
2023-08-22aarch64: Improve naming conventions for A and R-profile architectureVictor Do Nascimento1-135/+135
2023-03-30aarch64: Add the RPRFM instructionRichard Sandiford1-0/+23
2023-03-30aarch64: Add new SVE dot-product instructionsRichard Sandiford1-0/+3
2023-03-30aarch64: Add the SME2 shift instructionsRichard Sandiford1-0/+12
2023-03-30aarch64: Add the SME2 saturating conversion instructionsRichard Sandiford1-0/+1
2023-03-30aarch64: Add the SME2 MLALL and MLSLL instructionsRichard Sandiford1-0/+22
2023-03-30aarch64: Add the SME2 MLAL and MLSL instructionsRichard Sandiford1-0/+21
2023-03-30aarch64: Add the SME2 FMLA and FMLS instructionsRichard Sandiford1-0/+12
2023-03-30aarch64: Add the SME2 ADD and SUB instructionsRichard Sandiford1-17/+54
2023-03-30aarch64: Add the SME2 ZT0 instructionsRichard Sandiford1-2/+57
2023-03-30aarch64: Add the SME2 predicate-related instructionsRichard Sandiford1-4/+58
2023-03-30aarch64: Add the SME2 multivector LD1 and ST1 instructionsRichard Sandiford1-4/+44
2023-03-30aarch64: Add the SME2 MOVA instructionsRichard Sandiford1-4/+75
2023-03-30aarch64: Add support for predicate-as-counter registersRichard Sandiford1-0/+13
2023-03-30aarch64; Add support for vector offset rangesRichard Sandiford1-9/+48
2023-03-30aarch64: Add support for vgx2 and vgx4Richard Sandiford1-8/+41
2023-03-30aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_arrayRichard Sandiford1-3/+3
2023-03-30aarch64: Add a _10 suffix to FLD_imm3Richard Sandiford1-1/+1
2023-03-30aarch64: Prefer register ranges & support wrappingRichard Sandiford1-1/+1
2023-03-30aarch64: Add support for strided register listsRichard Sandiford1-23/+51
2023-03-30aarch64: Sort fields alphanumericallyRichard Sandiford1-81/+81
2023-03-30aarch64: Resync field namesRichard Sandiford1-7/+7
2023-03-30aarch64: Regularise FLD_* suffixesRichard Sandiford1-8/+8
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