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path: root/opcodes/aarch64-opc.c
AgeCommit message (Expand)AuthorFilesLines
2018-01-03Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2017-12-19Correct disassembly of dot product instructions.Tamar Christina1-0/+1
2017-12-19Add support for V_4B so we can properly reject it.Tamar Christina1-0/+1
2017-11-09Add assembler and disassembler support for the new Armv8.4-a registers for AA...Tamar Christina1-1/+147
2017-11-09Adds the new Fields and Operand types for the new instructions in Armv8.4-a.Tamar Christina1-0/+9
2017-09-25Initialize 'imm' on opcodes/aarch64-opc.c:expand_fp_imm (and fix breakage on ...Sergio Durigan Junior1-1/+1
2017-07-18Fix spelling typos.Yuri Chornovian1-1/+1
2017-05-18Don't compare boolean values against TRUE or FALSEAlan Modra1-4/+4
2017-04-24Fix snafu in aarch64 opcodes debugging statement.Tamar Christina1-2/+2
2017-02-24[AArch64] Additional SVE instructionsRichard Sandiford1-0/+39
2017-02-15[AArch64] Add SVE system registersRichard Sandiford1-0/+16
2017-02-03Fix compile time warning messages when compiling binutils with gcc 7.0.1.Nick Clifton1-2/+4
2017-01-02Update year range in copyright notice of all files.Alan Modra1-1/+1
2016-12-13[Binutils][AARCH64]Remove Cn register for coprocessor CRn, CRm fieldRenlin Li1-13/+4
2016-11-18[AArch64] Add ARMv8.3 FCMLA and FCADD instructionsSzabolcs Nagy1-2/+38
2016-11-18[AArch64] Add ARMv8.3 combined pointer authentication load instructionsSzabolcs Nagy1-0/+24
2016-11-11[AArch64] Add ARMv8.3 PACGA instructionSzabolcs Nagy1-0/+1
2016-11-11[AArch64] Add ARMv8.3 pointer authentication key registersSzabolcs Nagy1-0/+24
2016-10-07[AArch64] PR target/20667, fix disassembler for the "special" optional SYS_Rt...Jiong Wang1-4/+8
2016-10-06-Wimplicit-fallthrough warning fixesAlan Modra1-1/+6
2016-09-21[AArch64] Print spaces after commas in addressesRichard Sandiford1-8/+8
2016-09-21[AArch64] Use "must" rather than "should" in error messagesRichard Sandiford1-3/+3
2016-09-21[AArch64] Add SVE condition codesRichard Sandiford1-11/+22
2016-09-21[AArch64][SVE 30/32] Add SVE instruction classesRichard Sandiford1-0/+7
2016-09-21[AArch64][SVE 29/32] Add new SVE core & FP register operandsRichard Sandiford1-0/+11
2016-09-21[AArch64][SVE 28/32] Add SVE FP immediate operandsRichard Sandiford1-0/+43
2016-09-21[AArch64][SVE 27/32] Add SVE integer immediate operandsRichard Sandiford1-1/+189
2016-09-21[AArch64][SVE 26/32] Add SVE MUL VL addressing modesRichard Sandiford1-2/+59
2016-09-21[AArch64][SVE 25/32] Add support for SVE addressing modesRichard Sandiford1-2/+182
2016-09-21[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALEDRichard Sandiford1-5/+49
2016-09-21[AArch64][SVE 23/32] Add SVE pattern and prfop operandsRichard Sandiford1-1/+89
2016-09-21[AArch64][SVE 22/32] Add qualifiers for merging and zeroing predicationRichard Sandiford1-0/+7
2016-09-21[AArch64][SVE 21/32] Add Zn and Pn registersRichard Sandiford1-0/+93
2016-09-21[AArch64][SVE 20/32] Add support for tied operandsRichard Sandiford1-0/+17
2016-09-21[AArch64][SVE 19/32] Refactor address-printing codeRichard Sandiford1-36/+56
2016-09-21[AArch64][SVE 18/32] Tidy definition of aarch64-opc.c:int_regRichard Sandiford1-18/+11
2016-09-21[AArch64][SVE 17/32] Add a prefix parameter to print_register_listRichard Sandiford1-13/+16
2016-09-21[AArch64][SVE 14/32] Make aarch64_logical_immediate_p take an element sizeRichard Sandiford1-27/+28
2016-09-21[AArch64][SVE 13/32] Add an F_STRICT flagRichard Sandiford1-1/+10
2016-06-28[AArch64] Make register indices be full 64-bit valuesRichard Sandiford1-2/+12
2016-05-03Fix generation of AArhc64 instruction table.Szabolcs Nagy1-1/+2
2016-04-28Add support to AArch64 disassembler for verifying instructions. Add verifier...Nick Clifton1-0/+28
2016-03-24More -Wstack-usage warnings: opcodes/aarch64-*Jan Kratochvil1-4/+3
2016-01-20[AArch64] Reject invalid immediate operands to MSR UAOMatthew Wahab1-2/+4
2016-01-14[AArch64] Fix missing architecture checks for ARMv8.2 system registers.Matthew Wahab1-9/+7
2016-01-01Copyright update for binutilsAlan Modra1-1/+1
2015-12-14[AArch64][PATCH 11/14] Add support for the 2H vector type.Matthew Wahab1-0/+1
2015-12-14[AArch64] Fix errors rebasing the ARMv8.2 AT and system registers patchMatthew Wahab1-6/+7
2015-12-11[AArch64][Patch 5/5] Add instruction PSB CSYNCMatthew Wahab1-0/+5
2015-12-11[AArch64][Patch 4/5] Support HINT aliases taking operands.Matthew Wahab1-0/+12
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