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path: root/opcodes/aarch64-opc.c
AgeCommit message (Expand)AuthorFilesLines
2023-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2022-11-14aarch64: Add support for Common Short Sequence Compression extensionAndre Vieira1-0/+5
2022-10-17aarch64: Tweak handling of F_STRICTRichard Sandiford1-17/+8
2022-07-29libopcodes/aarch64: add support for disassembler stylingAndrew Burgess1-145/+300
2022-06-29opcodes/aarch64: split off creation of comment text in disassemblerAndrew Burgess1-6/+16
2022-03-31aarch64: Relax check for RNG system registersRichard Sandiford1-1/+1
2022-01-02Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2021-12-03aarch64: Fix uninitialised memoryRichard Sandiford1-0/+2
2021-12-02aarch64: Enforce P/M/E order for MOPS instructionsRichard Sandiford1-5/+90
2021-12-02aarch64: Add support for +mopsRichard Sandiford1-0/+41
2021-12-02aarch64: Add Armv8.8-A system registersRichard Sandiford1-0/+5
2021-12-02aarch64: Add id_aa64isar2_el1Richard Sandiford1-0/+1
2021-12-02aarch64: Tweak insn sequence codeRichard Sandiford1-26/+22
2021-12-02aarch64: Add maximum immediate value to aarch64_sys_regRichard Sandiford1-35/+22
2021-11-30aarch64: Add missing system registers [PR27145]Richard Sandiford1-1/+166
2021-11-30aarch64: Make LOR registers conditional on +lorRichard Sandiford1-4/+6
2021-11-30aarch64: Remove ZIDR_EL1Richard Sandiford1-1/+0
2021-11-30aarch64: Allow writes to MFAR_EL3Richard Sandiford1-1/+1
2021-11-30aarch64: Mark PMSIDR_EL1 as read-onlyRichard Sandiford1-1/+1
2021-11-30aarch64: Remove duplicate system register entriesRichard Sandiford1-7/+1
2021-11-25Fix building the AArch64 assembler and disassembler when assertions are disab...Nick Clifton1-3/+8
2021-11-17aarch64: [SME] SVE2 instructions added to support SMEPrzemyslaw Wirkus1-0/+12
2021-11-17aarch64: [SME] Add new SME system registersPrzemyslaw Wirkus1-1/+11
2021-11-17aarch64: [SME] Add SME mode selection and state access instructionsPrzemyslaw Wirkus1-4/+27
2021-11-17aarch64: [SME] Add LD1x, ST1x, LDR and STR instructionsPrzemyslaw Wirkus1-15/+67
2021-11-17aarch64: [SME] Add ZERO instructionPrzemyslaw Wirkus1-0/+45
2021-11-17aarch64: [SME] Add MOV and MOVA instructionsPrzemyslaw Wirkus1-0/+15
2021-11-17aarch64: [SME] Add SME instructionsPrzemyslaw Wirkus1-0/+11
2021-04-19aarch64: New instructions for maintenance of GPT entries cached in a TLBPrzemyslaw Wirkus1-0/+5
2021-04-19aarch64: Add new data cache maintenance operationsPrzemyslaw Wirkus1-0/+2
2021-04-16aarch64: Define RME system registersPrzemyslaw Wirkus1-0/+4
2021-03-31Use bool in opcodesAlan Modra1-68/+68
2021-03-31Remove bfd_stdint.hAlan Modra1-1/+1
2021-03-29TRUE/FALSE simplificationAlan Modra1-30/+24
2021-03-12aarch64: Add few missing system registersPrzemyslaw Wirkus1-0/+10
2021-01-11aarch64: Remove support for CSREKyrylo Tkachov1-4/+0
2021-01-08Treat the AArch64 register id_aa64mmfr2_el1 as a core system register.Nick Clifton1-1/+1
2021-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2020-11-09aarch64: Update LS64 feature with system registerPrzemyslaw Wirkus1-0/+2
2020-11-09aarch64: Limit Rt register number for LS64 load/store instructionsPrzemyslaw Wirkus1-0/+1
2020-11-04aarch64: Update feature RAS system registersPrzemyslaw Wirkus1-0/+5
2020-10-28aarch64: Add CSR PDEC instructionPrzemyslaw Wirkus1-0/+4
2020-10-28aarch64: Add DSB instruction Armv8.7-a variantPrzemyslaw Wirkus1-0/+10
2020-10-22[PATCH][GAS][AArch64] Define BRBE system registersPrzemyslaw Wirkus1-0/+106
2020-10-22aarch64: Define CSRE system registersPrzemyslaw Wirkus1-0/+13
2020-09-28This patch introduces ETMv4 (Embedded Trace Macrocell) system registers for t...Przemyslaw Wirkus1-0/+216
2020-09-28This patch introduces ETE (Embedded Trace Extension) system registers for the...Przemyslaw Wirkus1-0/+6
2020-09-28This patch introduces TRBE (Trace Buffer Extension) system registers for the ...Przemyslaw Wirkus1-0/+8
2020-09-08aarch64: Add support for Armv8-R system registersAlex Coplan1-9/+70
2020-08-12aarch64: Add support for MPAM system registersAlex Coplan1-0/+17
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