| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 7/9] Add BTI instruction | Sudakshina Das | 1 | -8/+9 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 4/9] Add Execution and Data Restriction instructions | Sudakshina Das | 1 | -8/+9 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 3/9] Add instruction SB for ARMv8.5-A | Sudakshina Das | 1 | -8/+8 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 2/9] Add Data procoessing instructions for ARMv8.5-A | Sudakshina Das | 1 | -69/+69 |
| 2018-07-12 | This patch adds support for the SSBB and PSSBB speculation barrier instructio... | Nick Clifton | 1 | -8/+8 |
| 2018-06-29 | Fix AArch64 encodings for by element instructions. | Tamar Christina | 1 | -0/+1 |
| 2018-03-28 | Enhance the AARCH64 assembler to support LDFF1xx instructions which use REG+R... | Nick Clifton | 1 | -0/+1 |
| 2018-01-09 | Add support for the AArch64's CSDB instruction. | James Greenhalgh | 1 | -8/+8 |
| 2018-01-03 | Update year range in copyright notice of binutils files | Alan Modra | 1 | -1/+1 |
| 2017-11-09 | Adds the new Fields and Operand types for the new instructions in Armv8.4-a. | Tamar Christina | 1 | -0/+5 |
| 2017-02-24 | [AArch64] Additional SVE instructions | Richard Sandiford | 1 | -0/+6 |
| 2017-01-02 | Update year range in copyright notice of all files. | Alan Modra | 1 | -1/+1 |
| 2016-12-13 | [Binutils][AARCH64]Remove Cn register for coprocessor CRn, CRm field | Renlin Li | 1 | -2/+2 |
| 2016-11-18 | [AArch64] Add ARMv8.3 FCMLA and FCADD instructions | Szabolcs Nagy | 1 | -53/+57 |
| 2016-11-18 | [AArch64] Add ARMv8.3 weaker release consistency load instructions | Szabolcs Nagy | 1 | -18/+18 |
| 2016-11-18 | [AArch64] Add ARMv8.3 javascript floating-point conversion instruction | Szabolcs Nagy | 1 | -25/+25 |
| 2016-11-18 | [AArch64] Add ARMv8.3 combined pointer authentication load instructions | Szabolcs Nagy | 1 | -15/+16 |
| 2016-11-11 | [AArch64] Add ARMv8.3 combined pointer authentication branch instructions | Szabolcs Nagy | 1 | -52/+52 |
| 2016-11-11 | [AArch64] Add ARMv8.3 PACGA instruction | Szabolcs Nagy | 1 | -26/+27 |
| 2016-11-11 | [AArch64] Add ARMv8.3 single source PAC instructions | Szabolcs Nagy | 1 | -49/+49 |
| 2016-11-11 | [AArch64] Add ARMv8.3 instructions which are in the NOP space | Szabolcs Nagy | 1 | -10/+10 |
| 2016-09-21 | [AArch64][SVE 31/32] Add SVE instructions | Richard Sandiford | 1 | -0/+11 |
| 2016-09-21 | [AArch64][SVE 29/32] Add new SVE core & FP register operands | Richard Sandiford | 1 | -0/+6 |
| 2016-09-21 | [AArch64][SVE 28/32] Add SVE FP immediate operands | Richard Sandiford | 1 | -0/+4 |
| 2016-09-21 | [AArch64][SVE 27/32] Add SVE integer immediate operands | Richard Sandiford | 1 | -0/+18 |
| 2016-09-21 | [AArch64][SVE 26/32] Add SVE MUL VL addressing modes | Richard Sandiford | 1 | -0/+6 |
| 2016-09-21 | [AArch64][SVE 25/32] Add support for SVE addressing modes | Richard Sandiford | 1 | -0/+31 |
| 2016-09-21 | [AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALED | Richard Sandiford | 1 | -0/+1 |
| 2016-09-21 | [AArch64][SVE 23/32] Add SVE pattern and prfop operands | Richard Sandiford | 1 | -0/+2 |
| 2016-09-21 | [AArch64][SVE 21/32] Add Zn and Pn registers | Richard Sandiford | 1 | -0/+18 |
| 2016-01-01 | Copyright update for binutils | Alan Modra | 1 | -1/+1 |
| 2015-12-14 | [AArch64][PATCH 14/14] Support FP16 Adv.SIMD Scalar Shift By Immediate instru... | Matthew Wahab | 1 | -43/+43 |
| 2015-12-14 | [AArch64][PATCH 13/14] Support FP16 Adv.SIMD Shift By Immediate instructions. | Matthew Wahab | 1 | -45/+45 |
| 2015-12-14 | [AArch64][PATCH 12/14] Support FP16 Adv.SIMD Scalar Pairwise instructions. | Matthew Wahab | 1 | -43/+43 |
| 2015-12-14 | [AArch64][PATCH 9/14] Support FP16 Adv.SIMD Modified Immediate instructions. | Matthew Wahab | 1 | -37/+37 |
| 2015-12-14 | [AArch64][PATCH 8/14] Support FP16 Adv.SIMD Across Lanes instructions. | Matthew Wahab | 1 | -53/+53 |
| 2015-12-14 | [AArch64][PATCH 7/14] Support FP16 Scalar Indexed Element instructions. | Matthew Wahab | 1 | -44/+44 |
| 2015-12-14 | [AArch64][PATCH 6/14] Support FP16 Vector Indexed Element instructions. | Matthew Wahab | 1 | -53/+53 |
| 2015-12-14 | [AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions. | Matthew Wahab | 1 | -56/+56 |
| 2015-12-14 | [AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions. | Matthew Wahab | 1 | -56/+56 |
| 2015-12-14 | [AArch64][PATCH 3/14] Support ARMv8.2 FP16 Scalar Three Same instructions. | Matthew Wahab | 1 | -50/+50 |
| 2015-12-14 | [AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions. | Matthew Wahab | 1 | -57/+57 |
| 2015-12-11 | [AArch64][Patch 5/5] Add instruction PSB CSYNC | Matthew Wahab | 1 | -0/+1 |
| 2015-12-11 | [AArch64][Patch 4/5] Support HINT aliases taking operands. | Matthew Wahab | 1 | -2/+2 |
| 2015-11-27 | [AArch64][PATCH 3/3] Add floating-point FP16 instructions | Matthew Wahab | 1 | -34/+34 |
| 2015-11-27 | [AArch64] Add ARMv8.2 instruction alias REV64. | Matthew Wahab | 1 | -18/+18 |
| 2015-11-27 | [AArch64] Add ARMv8.2 instructions BFC and REV64. | Matthew Wahab | 1 | -27/+28 |
| 2015-06-02 | [AArch64] Support for ARMv8.1a Adv.SIMD instructions | Matthew Wahab | 1 | -54/+54 |
| 2015-06-02 | [AArch64] Support for ARMv8.1a Limited Ordering Regions extension | Matthew Wahab | 1 | -12/+12 |
| 2015-03-10 | [AARCH64] Remove Load/Store register (unscaled immediate) alias. | Jiong Wang | 1 | -19/+19 |
