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2023-08-22aarch64: Improve naming conventions for A and R-profile architectureVictor Do Nascimento1-2/+2
Historically, flags and variables relating to architectural revisions for the A-profile architecture omitted the trailing `A' such that, for example, assembling for `-march=armv8.4-a' set the `AARCH64_ARCH_V8_4' flag in the assembler. This leads to some ambiguity, since Binutils also targets the R-profile Arm architecture. Therefore, it seems prudent to have everything associated with the A-profile cores end in `A' and likewise `R' for the R-profile. Referring back to the example above, the flag set for `-march=armv8.4-a' is better characterized if labeled `AARCH64_ARCH_V8_4A'. The only exception to the rule of appending `A' to variables is found in the handling of the `AARCH64_FEATURE_V8' macro, as it is the baseline from which ALL processors derive and should therefore be left unchanged. In reflecting the `ARM' architectural nomenclature choices, where we have `ARM_ARCH_V8A' and `ARM_ARCH_V8R', the choice is made to not have an underscore separating the numerical revision number and the A/R-profile indicator suffix. This has meant that renaming of R-profile related flags and variables was warranted, thus going from `.*_[vV]8_[rR]' to `.*_[vV]8[rR]'. Finally, this is more in line with conventions within GCC and adds consistency across the toolchain. gas/ChangeLog: * gas/config/tc-aarch64.c: (aarch64_cpus): Reference to arch feature macros updated. (aarch64_archs): Likewise. include/ChangeLog: * include/opcode/aarch64.h: (AARCH64_FEATURE_V8A): Updated name: V8_A -> V8A. (AARCH64_FEATURE_V8_1A): A-suffix added. (AARCH64_FEATURE_V8_2A): Likewise. (AARCH64_FEATURE_V8_3A): Likewise. (AARCH64_FEATURE_V8_4A): Likewise. (AARCH64_FEATURE_V8_5A): Likewise. (AARCH64_FEATURE_V8_6A): Likewise. (AARCH64_FEATURE_V8_7A): Likewise. (AARCH64_FEATURE_V8_8A):Likewise. (AARCH64_FEATURE_V9A): Likewise. (AARCH64_FEATURE_V8R): Updated name: V8_R -> V8R. (AARCH64_ARCH_V8A_FEATURES): Updated name: V8_A -> V8A. (AARCH64_ARCH_V8_1A_FEATURES): A-suffix added. (AARCH64_ARCH_V8_2A_FEATURES): Likewise. (AARCH64_ARCH_V8_3A_FEATURES): Likewise. (AARCH64_ARCH_V8_4A_FEATURES): Likewise. (AARCH64_ARCH_V8_5A_FEATURES): Likewise. (AARCH64_ARCH_V8_6A_FEATURES): Likewise. (AARCH64_ARCH_V8_7A_FEATURES): Likewise. (AARCH64_ARCH_V8_8A_FEATURES): Likewise. (AARCH64_ARCH_V9A_FEATURES): Likewise. (AARCH64_ARCH_V9_1A_FEATURES): Likewise. (AARCH64_ARCH_V9_2A_FEATURES): Likewise. (AARCH64_ARCH_V9_3A_FEATURES): Likewise. (AARCH64_ARCH_V8A): Updated name: V8_A -> V8A. (AARCH64_ARCH_V8_1A): A-suffix added. (AARCH64_ARCH_V8_2A): Likewise. (AARCH64_ARCH_V8_3A): Likewise. (AARCH64_ARCH_V8_4A): Likewise. (AARCH64_ARCH_V8_5A): Likewise. (AARCH64_ARCH_V8_6A): Likewise. (AARCH64_ARCH_V8_7A): Likewise. (AARCH64_ARCH_V8_8A): Likewise. (AARCH64_ARCH_V9A): Likewise. (AARCH64_ARCH_V9_1A): Likewise. (AARCH64_ARCH_V9_2A): Likewise. (AARCH64_ARCH_V9_3A): Likewise. (AARCH64_ARCH_V8_R): Updated name: V8_R -> V8R. opcodes/ChangeLog: * opcodes/aarch64-opc.c (SR_V8A): Updated name: V8_A -> V8A. (SR_V8_1A): A-suffix added. (SR_V8_2A): Likewise. (SR_V8_3A): Likewise. (SR_V8_4A): Likewise. (SR_V8_6A): Likewise. (SR_V8_7A): Likewise. (SR_V8_8A): Likewise. (aarch64_sys_regs): Reference to arch feature macros updated. (aarch64_pstatefields): Reference to arch feature macros updated. (aarch64_sys_ins_reg_supported_p): Reference to arch feature macros updated. * opcodes/aarch64-tbl.h: (aarch64_feature_v8_2a): a-suffix added. (aarch64_feature_v8_3a): Likewise. (aarch64_feature_fp_v8_3a): Likewise. (aarch64_feature_v8_4a): Likewise. (aarch64_feature_fp_16_v8_2a): Likewise. (aarch64_feature_v8_5a): Likewise. (aarch64_feature_v8_6a): Likewise. (aarch64_feature_v8_7a): Likewise. (aarch64_feature_v8r): Updated name: v8_r-> v8r. (ARMV8R): Updated name: V8_R-> V8R. (ARMV8_2A): A-suffix added. (ARMV8_3A): Likewise. (FP_V8_3A): Likewise. (ARMV8_4A): Likewise. (FP_F16_V8_2A): Likewise. (ARMV8_5): Likewise. (ARMV8_6A): Likewise. (ARMV8_6A_SVE): Likewise. (ARMV8_7A): Likewise. (V8_2A_INSN): `A' added to macro symbol. (V8_3A_INSN): Likewise. (V8_4A_INSN): Likewise. (FP16_V8_2A_INSN): Likewise. (V8_5A_INSN): Likewise. (V8_6A_INSN): Likewise. (V8_7A_INSN): Likewise. (V8R_INSN): Updated name: V8_R-> V8R.
2023-03-30aarch64: Add the SME2 shift instructionsRichard Sandiford1-0/+17
There are two instruction formats here: - SQRSHR, SQRSHRU and UQRSHR, which operate on lists of two or four registers. - SQRSHRN, SQRSHRUN and UQRSHRN, which operate on lists of four registers. These are the first SME2 instructions to have immediate operands. The patch makes sure that, when parsing SME2 instructions with immediate operands, the new predicate-as-counter registers are parsed as registers rather than as #-less immediates.
2023-03-30aarch64: Add the SME2 saturating conversion instructionsRichard Sandiford1-0/+4
There are two instruction formats here: - SQCVT, SQCVTU and UQCVT, which operate on lists of two or four registers. - SQCVTN, SQCVTUN and UQCVTN, which operate on lists of four registers.
2023-03-30aarch64: Add the SME2 MLAL and MLSL instructionsRichard Sandiford1-2/+6
The {BF,F,S,U}MLAL and {BF,F,S,U}MLSL instructions share the same encoding. They are the first instance of a ZA (as opposed to ZA tile) operand having a range of offsets. As with ZA tiles, the expected range size is encoded in the operand-specific data field.
2023-03-30aarch64: Add the SME2 maximum/minimum instructionsRichard Sandiford1-0/+7
This patch adds the SME2 multi-register forms of F{MAX,MIN}{,NM} and {S,U}{MAX,MIN}. SQDMULH, SRSHL and URSHL have the same form as SMAX etc., so the patch adds them too.
2023-03-30aarch64: Add the SME2 ADD and SUB instructionsRichard Sandiford1-0/+2
Add support for the SME2 ADD. SUB, FADD and FSUB instructions. SUB and FSUB have the same form as ADD and FADD, except that ADD also has a 2-operand accumulating form. The 64-bit ADD/SUB instructions require FEAT_SME_I16I64 and the 64-bit FADD/FSUB instructions require FEAT_SME_F64F64. These are the first instructions to have tied register list operands, as opposed to tied single registers. The parse_operands change prevents unsuffixed Z registers (width==-1) from being treated as though they had an Advanced SIMD-style suffix (.4s etc.). It means that: Error: expected element type rather than vector type at operand 2 -- `add za\.s\[w8,0\],{z0-z1}' becomes: Error: missing type suffix at operand 2 -- `add za\.s\[w8,0\],{z0-z1}'
2023-03-30aarch64: Add the SME2 ZT0 instructionsRichard Sandiford1-0/+15
SME2 adds lookup table instructions for quantisation. They use a new lookup table register called ZT0. LUTI2 takes an unsuffixed SVE vector index of the form Zn[<imm>], which is the first time that this syntax has been used.
2023-03-30aarch64: Add the SME2 predicate-related instructionsRichard Sandiford1-4/+29
Implementation-wise, the main things to note here are: - the WHILE* instructions have forms that return a pair of predicate registers. This is the first time that we've had lists of predicate registers, and they wrap around after register 15 rather than after register 31. - the predicate-as-counter WHILE* instructions have a fourth operand that specifies the vector length. We can treat this as an enumeration, except that immediate values aren't allowed. - PEXT takes an unsuffixed predicate index of the form PN<n>[<imm>]. This is the first instance of a vector/predicate index having no suffix.
2023-03-30aarch64: Add the SME2 multivector LD1 and ST1 instructionsRichard Sandiford1-1/+20
SME2 adds LD1 and ST1 variants for lists of 2 and 4 registers. The registers can be consecutive or strided. In the strided case, 2-register lists have a stride of 8, starting at register x0xxx. 4-register lists have a stride of 4, starting at register x00xx. The instructions are predicated on a predicate-as-counter register in the range pn8-pn15. Although we already had register fields with upper bounds of 7 and 15, this is the first plain register operand to have a nonzero lower bound. The patch uses the operand-specific data field to record the minimum value, rather than having separate inserters and extractors for each lower bound. This in turn required adding an extra bit to the field.
2023-03-30aarch64: Add the SME2 MOVA instructionsRichard Sandiford1-1/+59
SME2 defines new MOVA instructions for moving multiple registers to and from ZA. As with SME, the instructions are also available through MOV aliases. One notable feature of these instructions (and many other SME2 instructions) is that some register lists must start at a multiple of the list's size. The patch uses the general error "start register out of range" when this constraint isn't met, rather than an error specifically about multiples. This ensures that the error is consistent between these simple consecutive lists and later strided lists, for which the requirements aren't a simple multiple.
2023-03-30aarch64: Add a _10 suffix to FLD_imm3Richard Sandiford1-2/+2
SME2 adds various new 3-bit immediate fields, so this patch adds an lsb position suffix to the name of the field that we already have.
2023-03-30aarch64: Add support for strided register listsRichard Sandiford1-0/+5
SME2 has instructions that accept strided register lists, such as { z0.s, z4.s, z8.s, z12.s }. The purpose of this patch is to extend binutils to support such lists. The parsing code already had (unused) support for strides of 2. The idea here is instead to accept all strides during parsing and reject invalid strides during constraint checking. The SME2 instructions that accept strided operands also have non-strided forms. The errors about invalid strides therefore take a bitmask of acceptable strides, which allows multiple possibilities to be summed up in a single message. I've tried to update all code that handles register lists.
2023-03-30aarch64: Regularise FLD_* suffixesRichard Sandiford1-5/+5
Some FLD_imm* suffixes used a counting scheme such as FLD_immN, FLD_immN_2, FLD_immN_3, etc., while others used the lsb as the suffix. The latter seems more mnemonic, and was a big help in doing the SME2 work. Similarly, the _10 suffix on FLD_SME_size_10 was nonobvious. Presumably it indicated a 2-bit field, but it actually starts in bit 22.
2023-03-30aarch64: Try to report invalid variants against the closest matchRichard Sandiford1-1/+2
If an instruction has invalid qualifiers, GAS would report the error against the final opcode entry that got to the qualifier- checking stage. It seems better to report the error against the opcode entry that had the closest match, just like we pick the closest match within an opcode entry for the "did you mean this?" message. This patch adds the number of invalid operands as an argument to AARCH64_OPDE_INVALID_VARIANT and then picks the AARCH64_OPDE_INVALID_VARIANT with the lowest argument.
2023-03-30aarch64: Rename za_tile_vector to za_indexRichard Sandiford1-17/+17
za_tile_vector is also used for indexing ZA as a whole, rather than just for indexing tiles. The former is more common than the latter in SME2, so this patch generalises the name to "indexed_za". The patch also names the associated structure, so that later patches can reuse it during parsing.
2023-03-30aarch64: Make SME instructions use F_STRICTRichard Sandiford1-47/+46
This patch makes all SME instructions use F_STRICT, so that qualifiers have to be provided explicitly rather than being inferred from other operands. The main change is to move the qualifier setting from the operand-level decoders to the opcode level. This is one step towards consolidating the ZA parsing code and extending it to handle SME2.
2023-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
The newer update-copyright.py fixes file encoding too, removing cr/lf on binutils/bfdtest2.c and ld/testsuite/ld-cygwin/exe-export.exp, and embedded cr in binutils/testsuite/binutils-all/ar.exp string match.
2022-07-29libopcodes/aarch64: add support for disassembler stylingAndrew Burgess1-32/+215
This commit enables disassembler styling for AArch64. After this commit it is possible to have objdump style AArch64 disassembler output (using --disassembler-color option). Once the required GDB patches are merged, GDB will also style the disassembler output. The changes to support styling are mostly split between two files opcodes/aarch64-dis.c and opcodes/aarch64-opc.c. The entry point for the AArch64 disassembler can be found in aarch64-dis.c, this file handles printing the instruction mnemonics, and assembler directives (e.g. '.byte', '.word', etc). Some operands, mostly relating to assembler directives are also printed from this file. This commit changes all of this to pass through suitable styling information. However, for most "normal" instructions, the instruction operands are printed using a two step process. From aarch64-dis.c, in the print_operands function, the function aarch64_print_operand is called, this function is in aarch64-opc.c, and converts an instruction operand into a string. Then, back in print_operands (aarch64-dis.c), the operand string is printed. Unfortunately, the string returned by aarch64_print_operand can be quite complex, it will include syntax elements, like '[' and ']', in addition to register names and immediate values. In some cases, a single operand will expand into what will appear (to the user) as multiple operands separated with a ','. This makes the task of styling more complex, all these different components need to by styled differently, so we need to get the styling information out of aarch64_print_operand in some way. The solution that I propose here is similar to the solution that I used for the i386 disassembler. Currently, aarch64_print_operand uses snprintf to write the operand text into a buffer provided by the caller. What I propose is that we pass an extra argument to the aarch64_print_operand function, this argument will be a structure, the structure contains a callback function and some state. When aarch64_print_operand needs to format part of its output this can be done by using the callback function within the new structure, this callback returns a string with special embedded markers that indicate which mode should be used for each piece of text. Back in aarch64-dis.c we can spot these special style markers and use this to split the disassembler output up and apply the correct style to each piece. To make aarch64-opc.c clearer a series of new static functions have been added, e.g. 'style_reg', 'style_imm', etc. Each of these functions formats a piece of text in a different style, 'register' and 'immediate' in this case. Here's an example taken from aarch64-opc.c of the new functions in use: snprintf (buf, size, "[%s, %s]!", style_reg (styler, base), style_imm (styler, "#%d", opnd->addr.offset.imm)); The aarch64_print_operand function is also called from the assembler to aid in printing diagnostic messages. Right now I have no plans to add styling to the assembler output, and so, the callback function used in the assembler ignores the styling information and just returns an plain string. I've used the source files in gas/testsuite/gas/aarch64/ for testing, and have manually gone through and checked that the styling looks reasonable, however, I'm not an AArch64 expert, so it is possible that the odd piece is styled incorrectly. Please point out any mistakes I've made. With objdump disassembler color turned off, there should be no change in the output after this commit.
2022-06-29opcodes/aarch64: split off creation of comment text in disassemblerAndrew Burgess1-2/+13
The function aarch64_print_operand (aarch64-opc.c) is responsible for converting an instruction operand into the textual representation of that operand. In some cases, a comment is included in the operand representation, though this (currently) only happens for the last operand of the instruction. In a future commit I would like to enable the new libopcodes styling for AArch64, this will allow objdump and GDB[1] to syntax highlight the disassembler output, however, having operands and comments combined in a single string like this makes such styling harder. In this commit, I propose to extend aarch64_print_operand to take a second buffer. Any comments for the instruction are written into this extra buffer. The two callers of aarch64_print_operand are then updated to pass an extra buffer, and print any resulting comment. In this commit no styling is added, that will come later. However, I have adjusted the output slightly. Before this commit some comments would be separated from the instruction operands with a tab character, while in other cases the comment was separated with two single spaces. After this commit I use a single tab character in all cases. This means a few test cases needed updated. If people would prefer me to move everyone to use the two spaces, then just let me know. Or maybe there was a good reason why we used a mix of styles, I could probably figure out a way to maintain the old output exactly if that is critical. Other than that, there should be no user visible changes after this commit. [1] GDB patches have not been merged yet, but have been posted to the GDB mailing list: https://sourceware.org/pipermail/gdb-patches/2022-June/190142.html
2022-01-02Update year range in copyright notice of binutils filesAlan Modra1-1/+1
The result of running etc/update-copyright.py --this-year, fixing all the files whose mode is changed by the script, plus a build with --enable-maintainer-mode --enable-cgen-maint=yes, then checking out */po/*.pot which we don't update frequently. The copy of cgen was with commit d1dd5fcc38ead reverted as that commit breaks building of bfp opcodes files.
2021-12-03aarch64: Fix uninitialised memoryRichard Sandiford1-1/+1
AARCH64_OPDE_EXPECTED_A_AFTER_B and AARCH64_OPDE_A_SHOULD_FOLLOW_B are not paired with an error string, but we had an assert that the error was nonnull. Previously this assert was testing uninitialised memory and so could pass or fail arbitrarily. opcodes/ * aarch64-opc.c (verify_mops_pme_sequence): Initialize the error field to null for AARCH64_OPDE_EXPECTED_A_AFTER_B and AARCH64_OPDE_A_SHOULD_FOLLOW_B. * aarch64-dis.c (print_verifier_notes): Move assert.
2021-12-02aarch64: Enforce P/M/E order for MOPS instructionsRichard Sandiford1-4/+23
The MOPS instructions should be used as a triple, such as: cpyfp [x0]!, [x1]!, x2! cpyfm [x0]!, [x1]!, x2! cpyfe [x0]!, [x1]!, x2! The registers should also be the same for each writeback operand. This patch adds a warning for code that doesn't follow this rule, along similar lines to the warning that we already emit for invalid uses of MOVPRFX. include/ * opcode/aarch64.h (C_SCAN_MOPS_P, C_SCAN_MOPS_M, C_SCAN_MOPS_E) (C_SCAN_MOPS_PME): New macros. (AARCH64_OPDE_A_SHOULD_FOLLOW_B): New aarch64_operand_error_kind. (AARCH64_OPDE_EXPECTED_A_AFTER_B): Likewise. (aarch64_operand_error): Make each data value a union between an int and a string. opcodes/ * aarch64-tbl.h (MOPS_CPY_OP1_OP2_INSN): Add scan flags. (MOPS_SET_OP1_OP2_INSN): Likewise. * aarch64-opc.c (set_out_of_range_error): Update after change to aarch64_operand_error. (set_unaligned_error, set_reg_list_error): Likewise. (init_insn_sequence): Use a 3-instruction sequence for MOPS P instructions. (verify_mops_pme_sequence): New function. (verify_constraints): Call it. * aarch64-dis.c (print_verifier_notes): Handle AARCH64_OPDE_A_SHOULD_FOLLOW_B and AARCH64_OPDE_EXPECTED_A_AFTER_B. gas/ * config/tc-aarch64.c (operand_mismatch_kind_names): Add entries for AARCH64_OPDE_A_SHOULD_FOLLOW_B and AARCH64_OPDE_EXPECTED_A_AFTER_B. (operand_error_higher_severity_p): Check that AARCH64_OPDE_A_SHOULD_FOLLOW_B and AARCH64_OPDE_EXPECTED_A_AFTER_B come between AARCH64_OPDE_RECOVERABLE and AARCH64_OPDE_SYNTAX_ERROR; their relative order is not significant. (record_operand_error_with_data): Update after change to aarch64_operand_error. (output_operand_error_record): Likewise. Handle AARCH64_OPDE_A_SHOULD_FOLLOW_B and AARCH64_OPDE_EXPECTED_A_AFTER_B. * testsuite/gas/aarch64/mops_invalid_2.s, testsuite/gas/aarch64/mops_invalid_2.d, testsuite/gas/aarch64/mops_invalid_2.l: New test.
2021-12-02aarch64: Add support for +mopsRichard Sandiford1-0/+11
This patch adds support for FEAT_MOPS, an Armv8.8-A extension that provides memcpy and memset acceleration instructions. I took the perhaps controversial decision to generate the individual instruction forms using macros rather than list them out individually. This becomes useful with a follow-on patch to check that code follows the correct P/M/E sequence. [https://developer.arm.com/documentation/ddi0596/2021-09/Base-Instructions?lang=en] include/ * opcode/aarch64.h (AARCH64_FEATURE_MOPS): New macro. (AARCH64_ARCH_V8_8): Make armv8.8-a imply AARCH64_FEATURE_MOPS. (AARCH64_OPND_MOPS_ADDR_Rd): New aarch64_opnd. (AARCH64_OPND_MOPS_ADDR_Rs): Likewise. (AARCH64_OPND_MOPS_WB_Rn): Likewise. opcodes/ * aarch64-asm.h (ins_x0_to_x30): New inserter. * aarch64-asm.c (aarch64_ins_x0_to_x30): New function. * aarch64-dis.h (ext_x0_to_x30): New extractor. * aarch64-dis.c (aarch64_ext_x0_to_x30): New function. * aarch64-tbl.h (aarch64_feature_mops): New feature set. (aarch64_feature_mops_memtag): Likewise. (MOPS, MOPS_MEMTAG, MOPS_INSN, MOPS_MEMTAG_INSN) (MOPS_CPY_OP1_OP2_PME_INSN, MOPS_CPY_OP1_OP2_INSN, MOPS_CPY_OP1_INSN) (MOPS_CPY_INSN, MOPS_SET_OP1_OP2_PME_INSN, MOPS_SET_OP1_OP2_INSN) (MOPS_SET_INSN): New macros. (aarch64_opcode_table): Add MOPS instructions. (aarch64_opcode_table): Add entries for AARCH64_OPND_MOPS_ADDR_Rd, AARCH64_OPND_MOPS_ADDR_Rs and AARCH64_OPND_MOPS_WB_Rn. * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_MOPS_ADDR_Rd, AARCH64_OPND_MOPS_ADDR_Rs and AARCH64_OPND_MOPS_WB_Rn. (verify_three_different_regs): New function. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. gas/ * doc/c-aarch64.texi: Document +mops. * config/tc-aarch64.c (parse_x0_to_x30): New function. (parse_operands): Handle AARCH64_OPND_MOPS_ADDR_Rd, AARCH64_OPND_MOPS_ADDR_Rs and AARCH64_OPND_MOPS_WB_Rn. (aarch64_features): Add "mops". * testsuite/gas/aarch64/mops.s, testsuite/gas/aarch64/mops.d: New test. * testsuite/gas/aarch64/mops_invalid.s, * testsuite/gas/aarch64/mops_invalid.d, * testsuite/gas/aarch64/mops_invalid.l: Likewise.
2021-11-25Fix building the AArch64 assembler and disassembler when assertions are ↵Nick Clifton1-16/+17
disabled. PR 28614 * aarch64-asm.c: Replace assert(0) with real code. * aarch64-dis.c: Likewise. * aarch64-opc.c: Likewise.
2021-11-17aarch64: [SME] SVE2 instructions added to support SMEPrzemyslaw Wirkus1-0/+43
This patch is adding new SVE2 instructions added to support SME extension. The following SVE2 instructions are added by the SME architecture: * PSEL, * REVD, SCLAMP and UCLAMP. gas/ChangeLog: * config/tc-aarch64.c (parse_sme_pred_reg_with_index): New parser. (parse_operands): New parser. * testsuite/gas/aarch64/sme-9-illegal.d: New test. * testsuite/gas/aarch64/sme-9-illegal.l: New test. * testsuite/gas/aarch64/sme-9-illegal.s: New test. * testsuite/gas/aarch64/sme-9.d: New test. * testsuite/gas/aarch64/sme-9.s: New test. include/ChangeLog: * opcode/aarch64.h (enum aarch64_opnd): New operand AARCH64_OPND_SME_PnT_Wm_imm. opcodes/ChangeLog: * aarch64-asm.c (aarch64_ins_sme_pred_reg_with_index): New inserter. * aarch64-dis.c (aarch64_ext_sme_pred_reg_with_index): New extractor. * aarch64-opc.c (aarch64_print_operand): Printout of OPND_SME_PnT_Wm_imm. * aarch64-opc.h (enum aarch64_field_kind): New bitfields FLD_SME_Rm, FLD_SME_i1, FLD_SME_tszh, FLD_SME_tszl. * aarch64-tbl.h (OP_SVE_NN_BHSD): New qualifier. (OP_SVE_QMQ): New qualifier. (struct aarch64_opcode): New instructions PSEL, REVD, SCLAMP and UCLAMP. aarch64-asm-2.c: Regenerate. aarch64-dis-2.c: Regenerate. aarch64-opc-2.c: Regenerate.
2021-11-17aarch64: [SME] Add SME mode selection and state access instructionsPrzemyslaw Wirkus1-2/+36
This patch is adding new SME mode selection and state access instructions: * Add SMSTART and SMSTOP instructions. * Add SVCR system register. gas/ChangeLog: * config/tc-aarch64.c (parse_sme_sm_za): New parser. (parse_operands): New parser. * testsuite/gas/aarch64/sme-8-illegal.d: New test. * testsuite/gas/aarch64/sme-8-illegal.l: New test. * testsuite/gas/aarch64/sme-8-illegal.s: New test. * testsuite/gas/aarch64/sme-8.d: New test. * testsuite/gas/aarch64/sme-8.s: New test. include/ChangeLog: * opcode/aarch64.h (enum aarch64_opnd): New operand AARCH64_OPND_SME_SM_ZA. (enum aarch64_insn_class): New instruction classes sme_start and sme_stop. opcodes/ChangeLog: * aarch64-asm.c (aarch64_ins_pstatefield): New inserter. (aarch64_ins_sme_sm_za): New inserter. * aarch64-dis.c (aarch64_ext_imm): New extractor. (aarch64_ext_pstatefield): New extractor. (aarch64_ext_sme_sm_za): New extractor. * aarch64-opc.c (operand_general_constraint_met_p): New pstatefield value for SME instructions. (aarch64_print_operand): Printout for OPND_SME_SM_ZA. (SR_SME): New register SVCR. * aarch64-opc.h (F_REG_IN_CRM): New register endcoding. * aarch64-opc.h (F_IMM_IN_CRM): New immediate endcoding. (PSTATE_ENCODE_CRM): Encode CRm field. (PSTATE_DECODE_CRM): Decode CRm field. (PSTATE_ENCODE_CRM_IMM): Encode CRm immediate field. (PSTATE_DECODE_CRM_IMM): Decode CRm immediate field. (PSTATE_ENCODE_CRM_AND_IMM): Encode CRm and immediate field. * aarch64-tbl.h (struct aarch64_opcode): New SMSTART and SMSTOP instructions. aarch64-asm-2.c: Regenerate. aarch64-dis-2.c: Regenerate. aarch64-opc-2.c: Regenerate.
2021-11-17aarch64: [SME] Add LD1x, ST1x, LDR and STR instructionsPrzemyslaw Wirkus1-0/+50
This patch is adding new loads and stores defined by SME instructions. gas/ChangeLog: * config/tc-aarch64.c (parse_sme_address): New parser. (parse_sme_za_hv_tiles_operand_with_braces): New parser. (parse_sme_za_array): New parser. (output_operand_error_record): Print error details if present. (parse_operands): Support new operands. * testsuite/gas/aarch64/sme-5-illegal.d: New test. * testsuite/gas/aarch64/sme-5-illegal.l: New test. * testsuite/gas/aarch64/sme-5-illegal.s: New test. * testsuite/gas/aarch64/sme-5.d: New test. * testsuite/gas/aarch64/sme-5.s: New test. * testsuite/gas/aarch64/sme-6-illegal.d: New test. * testsuite/gas/aarch64/sme-6-illegal.l: New test. * testsuite/gas/aarch64/sme-6-illegal.s: New test. * testsuite/gas/aarch64/sme-6.d: New test. * testsuite/gas/aarch64/sme-6.s: New test. * testsuite/gas/aarch64/sme-7-illegal.d: New test. * testsuite/gas/aarch64/sme-7-illegal.l: New test. * testsuite/gas/aarch64/sme-7-illegal.s: New test. * testsuite/gas/aarch64/sme-7.d: New test. * testsuite/gas/aarch64/sme-7.s: New test. include/ChangeLog: * opcode/aarch64.h (enum aarch64_opnd): New operands. (enum aarch64_insn_class): Added sme_ldr and sme_str. (AARCH64_OPDE_UNTIED_IMMS): New operand error kind. opcodes/ChangeLog: * aarch64-asm.c (aarch64_ins_sme_za_hv_tiles): New inserter. (aarch64_ins_sme_za_list): New inserter. (aarch64_ins_sme_za_array): New inserter. (aarch64_ins_sme_addr_ri_u4xvl): New inserter. * aarch64-asm.h (AARCH64_DECL_OPD_INSERTER): Added ins_sme_za_list, ins_sme_za_array and ins_sme_addr_ri_u4xvl. * aarch64-dis.c (aarch64_ext_sme_za_hv_tiles): New extractor. (aarch64_ext_sme_za_list): New extractor. (aarch64_ext_sme_za_array): New extractor. (aarch64_ext_sme_addr_ri_u4xvl): New extractor. * aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR): Added ext_sme_za_list, ext_sme_za_array and ext_sme_addr_ri_u4xvl. * aarch64-opc.c (operand_general_constraint_met_p): (aarch64_match_operands_constraint): Handle sme_ldr, sme_str and sme_misc. (aarch64_print_operand): New operands supported. * aarch64-tbl.h (OP_SVE_QUU): New qualifier. (OP_SVE_QZU): New qualifier. aarch64-asm-2.c: Regenerate. aarch64-dis-2.c: Regenerate. aarch64-opc-2.c: Regenerate.
2021-11-17aarch64: [SME] Add MOV and MOVA instructionsPrzemyslaw Wirkus1-0/+58
This patch is adding new MOV (alias) and MOVA SME instruction. gas/ChangeLog: * config/tc-aarch64.c (enum sme_hv_slice): new enum. (struct reloc_entry): Added ZAH and ZAV registers. (parse_sme_immediate): Immediate parser. (parse_sme_za_hv_tiles_operand): ZA tile parser. (parse_sme_za_hv_tiles_operand_index): Index parser. (parse_operands): Added ZA tile parser calls. (REGNUMS): New macro. Regs with suffix. (REGSET16S): New macro. 16 regs with suffix. * testsuite/gas/aarch64/sme-2-illegal.d: New test. * testsuite/gas/aarch64/sme-2-illegal.l: New test. * testsuite/gas/aarch64/sme-2-illegal.s: New test. * testsuite/gas/aarch64/sme-2.d: New test. * testsuite/gas/aarch64/sme-2.s: New test. * testsuite/gas/aarch64/sme-2a.d: New test. * testsuite/gas/aarch64/sme-2a.s: New test. * testsuite/gas/aarch64/sme-3-illegal.d: New test. * testsuite/gas/aarch64/sme-3-illegal.l: New test. * testsuite/gas/aarch64/sme-3-illegal.s: New test. * testsuite/gas/aarch64/sme-3.d: New test. * testsuite/gas/aarch64/sme-3.s: New test. * testsuite/gas/aarch64/sme-3a.d: New test. * testsuite/gas/aarch64/sme-3a.s: New test. include/ChangeLog: * opcode/aarch64.h (enum aarch64_opnd): New enums AARCH64_OPND_SME_ZA_HV_idx_src and AARCH64_OPND_SME_ZA_HV_idx_dest. (struct aarch64_opnd_info): New ZA tile vector struct. opcodes/ChangeLog: * aarch64-asm.c (aarch64_ins_sme_za_hv_tiles): New inserter. * aarch64-asm.h (AARCH64_DECL_OPD_INSERTER): New inserter ins_sme_za_hv_tiles. * aarch64-dis.c (aarch64_ext_sme_za_hv_tiles): New extractor. * aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR): New extractor ext_sme_za_hv_tiles. * aarch64-opc.c (aarch64_print_operand): Handle SME_ZA_HV_idx_src and SME_ZA_HV_idx_dest. * aarch64-opc.h (enum aarch64_field_kind): New enums FLD_SME_size_10, FLD_SME_Q, FLD_SME_V and FLD_SME_Rv. (struct aarch64_operand): Increase fields size to 5. * aarch64-tbl.h (OP_SME_BHSDQ_PM_BHSDQ): New qualifiers aarch64-asm-2.c: Regenerate. aarch64-dis-2.c: Regenerate. aarch64-opc-2.c: Regenerate.
2021-11-05Missing va_end in aarch64-dis.cAlan Modra1-0/+1
* aarch64-dis.c (extract_fields): Invoke va_end.
2021-03-31Use bool in opcodesAlan Modra1-212/+212
cpu/ * frv.opc: Replace bfd_boolean with bool, FALSE with false, and TRUE with true throughout. opcodes/ * sysdep.h (POISON_BFD_BOOLEAN): Define. * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h, * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h, * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c, * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c, * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c, * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c, * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c, * microblaze-dis.h, * micromips-opc.c, * mips-dis.c, * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c, * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c, * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c, * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c, * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false, and TRUE with true throughout.
2021-03-31Remove bfd_stdint.hAlan Modra1-1/+1
If we require C99 for binutils then stdint.h is available. bfd/ * .gitignore: Delete bfd_stdint.h entry. * Makefile.am (bfdinclude_HEADERS): Delete bfd_stdint.h. (BUILD_HFILES, LOCAL_H_DEPS): Likewise. * bfd-in.h: Include stdint.h in place of bfd_stdint.h. * configure.ac: Don't invoke GCC_HEADER_STDINT. * configure.com: Don't create bfd_stdint.h. * Makefile.in: Regenerate. * aclocal.m4: Regenerate. * bfd-in2.h: Regenerate. * config.in: Regenerate. * configure: Regenerate. * doc/Makefile.in: Regenerate. * po/BLD-POTFILES.in: Regenerate. binutils/ * coffdump.c: Include stdint.h in place of bfd_stdint.h. * dwarf.c: Likewise. gas/ * config/tc-aarch64.c: Include stdint.h in place of bfd_stdint.h. * config/tc-crx.c: Likewise. * config/tc-nds32.h: Likewise. include/ * cgen/basic-modes.h: Include stdint.h in place of bfd_stdint.h. * elf/nfp.h: Likewise. * opcode/aarch64.h: Likewise. * opcode/cgen.h: Likewise. * opcode/nfp.h: Likewise. * opcode/ppc.h: Likewise. ld/ * elf-hints-local.h: Include stdint.h in place of bfd_stdint.h. * emultempl/nds32elf.em: Likewise. * testsuite/ld-elf/mbind2b.c: Likewise. * testsuite/ld-elf/pr18718.c: Likewise. * testsuite/ld-elf/pr18720a.c: Likewise. * testsuite/ld-elf/pr25749-1.c: Likewise. * testsuite/ld-elf/pr25749-1a.c: Likewise. * testsuite/ld-elf/pr25749-1b.c: Likewise. * testsuite/ld-elf/pr25749-1c.c: Likewise. * testsuite/ld-elf/pr25749-1d.c: Likewise. * testsuite/ld-elf/pr25749-2.c: Likewise. * testsuite/ld-elf/pr25754-1a.c: Likewise. * testsuite/ld-elf/pr25754-2a.c: Likewise. * testsuite/ld-elf/pr25754-3a.c: Likewise. * testsuite/ld-elf/pr25754-4a.c: Likewise. * testsuite/ld-elf/pr25754-5a.c: Likewise. * testsuite/ld-elf/pr25754-6a.c: Likewise. opcodes/ * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h. * aarch64-dis.h: Likewise. * aarch64-opc.c: Likewise. * avr-dis.c: Likewise. * csky-dis.c: Likewise. * nds32-asm.c: Likewise. * nds32-dis.c: Likewise. * nfp-dis.c: Likewise. * riscv-dis.c: Likewise. * s12z-dis.c: Likewise. * wasm32-dis.c: Likewise.
2021-03-22Add startswith function and use it instead of CONST_STRNEQ.Martin Liska1-5/+5
bfd/ChangeLog: * bfd-in.h (startswith): Add startswith function. (CONST_STRNEQ): Remove. * bfd-in2.h (startswith): Regenerate with make headers. * archive.c (bfd_slurp_armap): Replace usage of CONST_STRNEQ with startswith. (_bfd_slurp_extended_name_table): Likewise. * archive64.c (_bfd_archive_64_bit_slurp_armap): Likewise. * bfd.c (bfd_get_sign_extend_vma): Likewise. (bfd_convert_section_size): Likewise. (bfd_convert_section_contents): Likewise. * coff-stgo32.c (go32exe_create_stub): Likewise. (go32exe_check_format): Likewise. * coffcode.h (styp_to_sec_flags): Likewise. (GNU_DEBUGALTLINK): Likewise. * coffgen.c (_bfd_coff_section_already_linked): Likewise. (coff_gc_sweep): Likewise. (bfd_coff_gc_sections): Likewise. * cofflink.c (coff_link_add_symbols): Likewise. (process_embedded_commands): Likewise. * compress.c (bfd_is_section_compressed_with_header): Likewise. (bfd_init_section_decompress_status): Likewise. * dwarf2.c (find_debug_info): Likewise. (place_sections): Likewise. * ecoff.c (_bfd_ecoff_slurp_armap): Likewise. * elf-m10300.c (_bfd_mn10300_elf_size_dynamic_sections): Likewise. * elf.c (_bfd_elf_make_section_from_shdr): Likewise. (assign_section_numbers): Likewise. (elfcore_grok_win32pstatus): Likewise. * elf32-arm.c (cmse_scan): Likewise. (elf32_arm_gc_mark_extra_sections): Likewise. (elf32_arm_size_dynamic_sections): Likewise. (is_arm_elf_unwind_section_name): Likewise. * elf32-bfin.c (bfin_size_dynamic_sections): Likewise. * elf32-cr16.c (_bfd_cr16_elf_size_dynamic_sections): Likewise. * elf32-cris.c (elf_cris_size_dynamic_sections): Likewise. * elf32-csky.c (csky_elf_size_dynamic_sections): Likewise. * elf32-hppa.c (elf32_hppa_size_dynamic_sections): Likewise. * elf32-iq2000.c (iq2000_elf_check_relocs): Likewise. * elf32-lm32.c (lm32_elf_size_dynamic_sections): Likewise. * elf32-m32r.c (m32r_elf_size_dynamic_sections): Likewise. * elf32-m68k.c (elf_m68k_size_dynamic_sections): Likewise. * elf32-metag.c (elf_metag_size_dynamic_sections): Likewise. * elf32-msp430.c (msp430_elf_relax_delete_bytes): Likewise. * elf32-nios2.c (nios2_elf32_size_dynamic_sections): Likewise. * elf32-or1k.c (or1k_elf_size_dynamic_sections): Likewise. * elf32-ppc.c (ppc_elf_size_dynamic_sections): Likewise. * elf32-s390.c (elf_s390_size_dynamic_sections): Likewise. * elf32-score.c (s3_bfd_score_elf_size_dynamic_sections): Likewise. * elf32-score7.c (s7_bfd_score_elf_size_dynamic_sections): Likewise. * elf32-sh.c (sh_elf_size_dynamic_sections): Likewise. * elf32-tic6x.c (is_tic6x_elf_unwind_section_name): Likewise. (elf32_tic6x_size_dynamic_sections): Likewise. * elf32-vax.c (elf_vax_size_dynamic_sections): Likewise. * elf32-xtensa.c (elf_xtensa_size_dynamic_sections): Likewise. (xtensa_is_insntable_section): Likewise. (xtensa_is_littable_section): Likewise. (xtensa_is_proptable_section): Likewise. (xtensa_property_section_name): Likewise. (xtensa_callback_required_dependence): Likewise. * elf64-alpha.c (elf64_alpha_size_dynamic_sections): Likewise. * elf64-hppa.c (elf64_hppa_size_dynamic_sections): Likewise. * elf64-ia64-vms.c (is_unwind_section_name): Likewise. (get_reloc_section): Likewise. (elf64_ia64_size_dynamic_sections): Likewise. (elf64_ia64_object_p): Likewise. * elf64-mmix.c (mmix_elf_add_symbol_hook): Likewise. * elf64-ppc.c (ppc64_elf_size_dynamic_sections): Likewise. * elf64-s390.c (elf_s390_size_dynamic_sections): Likewise. * elflink.c (elf_link_add_object_symbols): Likewise. (_bfd_elf_gc_mark_extra_sections): Likewise. (bfd_elf_parse_eh_frame_entries): Likewise. (_bfd_elf_section_already_linked): Likewise. * elfnn-aarch64.c (elfNN_aarch64_size_dynamic_sections): Likewise. * elfnn-ia64.c (is_unwind_section_name): Likewise. (elfNN_ia64_size_dynamic_sections): Likewise. (elfNN_ia64_object_p): Likewise. * elfxx-mips.c (FN_STUB_P): Likewise. (CALL_STUB_P): Likewise. (CALL_FP_STUB_P): Likewise. (_bfd_mips_elf_section_from_shdr): Likewise. (_bfd_mips_elf_fake_sections): Likewise. (_bfd_mips_elf_size_dynamic_sections): Likewise. (_bfd_mips_final_write_processing): Likewise. (_bfd_mips_elf_final_link): Likewise. * elfxx-sparc.c (_bfd_sparc_elf_size_dynamic_sections): Likewise. * elfxx-x86.c (elf_i386_is_reloc_section): Likewise. (elf_x86_64_is_reloc_section): Likewise. * hpux-core.c (thread_section_p): Likewise. * libcoff.h (bfd_pei_p): Likewise. * linker.c (REAL): Likewise. (unwrap_hash_lookup): Likewise. (_bfd_generic_link_add_one_symbol): Likewise. * mmo.c (mmo_internal_write_section): Likewise. * osf-core.c (osf_core_core_file_p): Likewise. * pef.c (bfd_pef_print_symbol): Likewise. * pei-x86_64.c (pex64_print_all_pdata_sections): Likewise. * som.c (som_slurp_symbol_table): Likewise. (som_slurp_armap): Likewise. * wasm-module.c (wasm_compute_custom_section_file_position): Likewise. binutils/ChangeLog: * dlltool.c (scan_drectve_symbols): Replace usage of CONST_STRNEQ with startswith. * emul_aix.c (ar_emul_aix_parse_arg): Likewise. * objcopy.c (is_mergeable_note_section): Likewise. * objdump.c (dump_dwarf_section): Likewise. * prdbg.c (pr_method_type): Likewise. (pr_class_baseclass): Likewise. (tg_class_baseclass): Likewise. * readelf.c (process_lto_symbol_tables): Likewise. * stabs.c (ULLHIGH): Likewise. (parse_stab_argtypes): Likewise. (stab_demangle_function_name): Likewise. gas/ChangeLog: * config/tc-i386.c (md_parse_option): Replace usage of CONST_STRNEQ with startswith. (x86_64_section_word): Likewise. * config/tc-sparc.c (md_parse_option): Likewise. gdb/ChangeLog: * arm-tdep.c (show_disassembly_style_sfunc): Replace usage of CONST_STRNEQ with startswith. (_initialize_arm_tdep): Likewise. ld/ChangeLog: * emultempl/aix.em: Replace usage of CONST_STRNEQ with startswith. * emultempl/beos.em: Likewise. * emultempl/elf.em: Likewise. * emultempl/pe.em: Likewise. * emultempl/pep.em: Likewise. * emultempl/xtensaelf.em: Likewise. * ldctor.c (ctor_prio): Likewise. * ldelf.c (ldelf_try_needed): Likewise. (ldelf_parse_ld_so_conf): Likewise. (ldelf_after_open): Likewise. (output_rel_find): Likewise. (ldelf_place_orphan): Likewise. * ldfile.c (ldfile_add_library_path): Likewise. * ldlang.c (lang_add_input_file): Likewise. * ldmain.c (get_sysroot): Likewise. (get_emulation): Likewise. (add_archive_element): Likewise. * ldwrite.c (unsplittable_name): Likewise. (clone_section): Likewise. * lexsup.c (parse_args): Likewise. * pe-dll.c (is_import): Likewise. (pe_implied_import_dll): Likewise. opcodes/ChangeLog: * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith. * arc-dis.c (parse_option): Likewise. * arm-dis.c (parse_arm_disassembler_options): Likewise. * cris-dis.c (print_with_operands): Likewise. * h8300-dis.c (bfd_h8_disassemble): Likewise. * i386-dis.c (print_insn): Likewise. * ia64-gen.c (fetch_insn_class): Likewise. (parse_resource_users): Likewise. (in_iclass): Likewise. (lookup_specifier): Likewise. (insert_opcode_dependencies): Likewise. * mips-dis.c (parse_mips_ase_option): Likewise. (parse_mips_dis_option): Likewise. * s390-dis.c (disassemble_init_s390): Likewise. * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
2021-01-08Fix places in the AArch64 opcodes library code where a call to assert() has ↵Nick Clifton1-1/+3
side effects. PR 27129 * aarch64-dis.c (determine_disassembling_preference): Move call to aarch64_match_operands_constraint outside of the assertion. * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert. Replace with a return of FALSE.
2021-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2020-10-28aarch64: Add DSB instruction Armv8.7-a variantPrzemyslaw Wirkus1-0/+15
This patch adds new variant (nXS) of DSB memory barrier instruction available in Armv8.7-a. New nXS variant has different encoding in comparison with pre Armv8.7-a DSB memory barrier variant thus new instruction and new operand was added. DSB memory nXS barrier variant specifies the limitation on the barrier operation. Allowed values are: DSB SYnXS|#28 DSB ISHnXS|#24 DSB NSHnXS|#20 DSB OSHnXS|#16 Please note that till now, for barriers, barrier operation was encoded in 4-bit unsigned immediate CRm field (in the range 0 to 15). For DSB memory nXS barrier variant, barrier operation is a 5-bit unsigned assembly instruction immediate, encoded in instruction in two bits CRm<3:2>: CRm<3:2> #imm 00 16 01 20 10 24 11 28 This patch extends current AArch64 barrier instructions with above mapping. Notable patch changes include: + New DSB memory barrier variant encoding for Armv8.7-a. + New operand BARRIER_DSB_NXS for above instruction in order to distinguish between existing and new DSB instruction flavour. + New set of DSB nXS barrier options. + New instruction inserter and extractor map between instruction immediate 5-bit value and 2-bit CRm field of the instruction itself (see FLD_CRm_dsb_nxs). + Regeneration of aarch64-[asm|dis|opc]-2.c files. + Test cases to cover new instruction assembling and disassembling. For more details regarding DSB memory barrier instruction and its Armv8.7-a flavour please refer to Arm A64 Instruction set documentation for Armv8-A architecture profile, see document pages 132-133 of [0]. [0]: https://developer.arm.com/docs/ddi0596/i gas/ChangeLog: 2020-10-23 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * NEWS: Docs update. * config/tc-aarch64.c (parse_operands): Add AARCH64_OPND_BARRIER_DSB_NXS handler. (md_begin): Add content of aarch64_barrier_dsb_nxs_options to aarch64_barrier_opt_hsh hash. * testsuite/gas/aarch64/system-4-invalid.d: New test. * testsuite/gas/aarch64/system-4-invalid.l: New test. * testsuite/gas/aarch64/system-4-invalid.s: New test. * testsuite/gas/aarch64/system-4.d: New test. * testsuite/gas/aarch64/system-4.s: New test. include/ChangeLog: 2020-10-23 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New operand AARCH64_OPND_BARRIER_DSB_NXS. (aarch64_barrier_dsb_nxs_options): Declare DSB nXS options. opcodes/ChangeLog: 2020-10-23 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * aarch64-asm.c (aarch64_ins_barrier_dsb_nxs): New inserter. * aarch64-asm.h (AARCH64_DECL_OPD_INSERTER): New inserter ins_barrier_dsb_nx. * aarch64-dis.c (aarch64_ext_barrier_dsb_nxs): New extractor. * aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR): New extractor ext_barrier_dsb_nx. * aarch64-opc.c (aarch64_print_operand): New options table aarch64_barrier_dsb_nxs_options. * aarch64-opc.h (enum aarch64_field_kind): New field name FLD_CRm_dsb_nxs. * aarch64-tbl.h (struct aarch64_opcode): Define DSB nXS barrier Armv8.7-a instruction. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated.
2020-09-08aarch64: Add support for Armv8-R system registersAlex Coplan1-1/+1
This patch adds support for the system registers introduced in Armv8-R AArch64. gas/ChangeLog: 2020-09-08 Alex Coplan <alex.coplan@arm.com> * config/tc-aarch64.c (parse_sys_reg): Also pass sysreg name to validation function. (parse_sys_ins_reg): Likewise. (print_operands): Pass CPU features to aarch64_print_operand(). * testsuite/gas/aarch64/v8-r-bad-sysregs.d: New test. * testsuite/gas/aarch64/v8-r-bad-sysregs.l: Error output. * testsuite/gas/aarch64/v8-r-bad-sysregs.s: Input. * testsuite/gas/aarch64/v8-r-sysregs-need-arch.d: New test. * testsuite/gas/aarch64/v8-r-sysregs-need-arch.l: Error output. * testsuite/gas/aarch64/v8-r-sysregs.d: New test. * testsuite/gas/aarch64/v8-r-sysregs.s: Input for previous two tests. include/ChangeLog: 2020-09-08 Alex Coplan <alex.coplan@arm.com> * opcode/aarch64.h (aarch64_sys_ins_reg_supported_p): Also take system register name in order to simplify validation for v8-R. (aarch64_print_operand): Also take CPU feature set, as disassembly for system registers now depends on arch variant. opcodes/ChangeLog: 2020-09-08 Alex Coplan <alex.coplan@arm.com> * aarch64-dis.c (print_operands): Pass CPU features to aarch64_print_operand(). * aarch64-opc.c (aarch64_print_operand): Use CPU features to determine preferred disassembly of system registers. (SR_RNG): Refactor to use new SR_FEAT2 macro. (SR_FEAT2): New. (SR_V8_1_A): New. (SR_V8_4_A): New. (SR_V8_A): New. (SR_V8_R): New. (SR_EXPAND_ELx): New. (SR_EXPAND_EL12): New. (aarch64_sys_regs): Specify which registers are only on A-profile, add R-profile system registers. (ENC_BARLAR): New. (PRBARn_ELx): New. (PRLARn_ELx): New. (aarch64_sys_ins_reg_supported_p): Reject EL3 registers for Armv8-R AArch64.
2020-09-08aarch64: Add base support for Armv8-RAlex Coplan1-0/+33
This patch adds the basic infrastructure needed to support Armv8-R in AArch64 binutils: new command-line flags, new feature bits, a new BFD architecture, and support for differentiating between architecture variants in the disassembler. The new command-line options added by this patch are -march=armv8-r in GAS and -m aarch64:armv8-r in objdump. The disassembler support is necessary since Armv8-R AArch64 introduces a system register (VSCTLR_EL2) which shares an encoding with a different system register (TTBR0_EL2) in Armv8-A. This also allows us to use the correct preferred disassembly for the new DFB alias introduced in Armv8-R. bfd/ChangeLog: 2020-09-08 Alex Coplan <alex.coplan@arm.com> * archures.c (bfd_mach_aarch64_8R): New. * bfd-in2.h: Regenerate. * cpu-aarch64.c (bfd_aarch64_arch_v8_r): New. (bfd_aarch64_arch_ilp32): Update tail pointer. gas/ChangeLog: 2020-09-08 Alex Coplan <alex.coplan@arm.com> * config/tc-aarch64.c (aarch64_archs): Add armv8-r. * doc/c-aarch64.texi: Document -march=armv8-r. include/ChangeLog: 2020-09-08 Alex Coplan <alex.coplan@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_V8_A): New. (AARCH64_FEATURE_V8_R): New. (AARCH64_ARCH_V8): Include new A-profile feature bit. (AARCH64_ARCH_V8_R): New. opcodes/ChangeLog: 2020-09-08 Alex Coplan <alex.coplan@arm.com> * aarch64-dis.c (arch_variant): New. (determine_disassembling_preference): Disassemble according to arch variant. (select_aarch64_variant): New. (print_insn_aarch64): Set feature set.
2020-08-21Fix problems with the AArch64 linker exposed by testing it with sanitization ↵Nick Clifton1-1/+9
enabled. bfd * elfnn-aarch64.c (_bfd_aarch64_erratum_835769_scan): Only sort the data map if there are entries in it. (_bfd_aarch64_erratum_843419_scan): Likewise. opcodes * aarch64-dis.c (get_sym_code_type): Return FALSE for non-ELF symbols.
2020-04-20[AArch64, Binutils] Add missing TSB instructionSudakshina Das1-0/+10
This patch implements the TSB instructions: https://developer.arm.com/docs/ddi0596/f/base-instructions-alphabetic-order/ tsb-csync-trace-synchronization-barrier Since TSB and PSB both use the same (and only) argument "CSYNC", this patch reuses it for TSB. However, the same argument would imply different value for CRm:Op2 which are anyway fixed values, so I have diverted the inserter/extracter function to dummy versions instead of the "hint" version. The operand checker part still uses the existing infratructure for AARCH64_OPND_BARRIER_PSB to make sure the operand is parsed correctly. gas/ChangeLog: 2020-04-20 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (parse_barrier_psb): Update error messages to include TSB. * testsuite/gas/aarch64/system-2.d: Update -march and new tsb tests. * testsuite/gas/aarch64/system-2.s: Add new tsb tests. * testsuite/gas/aarch64/system.d: Update. opcodes/ChangeLog: 2020-04-20 Sudakshina Das <sudi.das@arm.com> * aarch64-asm.c (aarch64_ins_none): New. * aarch64-asm.h (ins_none): New declaration. * aarch64-dis.c (aarch64_ext_none): New. * aarch64-dis.h (ext_none): New declaration. * aarch64-opc.c (aarch64_print_operand): Update case for AARCH64_OPND_BARRIER_PSB. * aarch64-tbl.h (aarch64_opcode_table): Add tsb. (AARCH64_OPERANDS): Update inserter/extracter for AARCH64_OPND_BARRIER_PSB to use new dummy functions. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated.
2020-02-26Indent labelsAlan Modra1-1/+1
Labels don't go in the first column according to standard emacs C indent rules, and I got annoyed enough at seeing diff -p show a label rather than the function name to fix this. bfd/ * aoutx.h: Indent labels correctly. Format error strings. * archive.c: Likewise. * archive64.c: Likewise. * coff-arm.c: Likewise. * coff-rs6000.c: Likewise. * coff-stgo32.c: Likewise. * cpu-arm.c: Likewise. * dwarf2.c: Likewise. * elf-ifunc.c: Likewise. * elf-properties.c: Likewise. * elf-s390-common.c: Likewise. * elf-strtab.c: Likewise. * elf.c: Likewise. * elf32-arm.c: Likewise. * elf32-bfin.c: Likewise. * elf32-cr16.c: Likewise. * elf32-csky.c: Likewise. * elf32-i386.c: Likewise. * elf32-m68k.c: Likewise. * elf32-msp430.c: Likewise. * elf32-nds32.c: Likewise. * elf32-nios2.c: Likewise. * elf32-pru.c: Likewise. * elf32-xtensa.c: Likewise. * elf64-ia64-vms.c: Likewise. * elf64-x86-64.c: Likewise. * elfcode.h: Likewise. * elfcore.h: Likewise. * elflink.c: Likewise. * elfnn-aarch64.c: Likewise. * elfnn-ia64.c: Likewise. * elfnn-riscv.c: Likewise. * elfxx-mips.c: Likewise. * elfxx-sparc.c: Likewise. * elfxx-x86.c: Likewise. * i386lynx.c: Likewise. * merge.c: Likewise. * pdp11.c: Likewise. * plugin.c: Likewise. * reloc.c: Likewise. binutils/ * elfedit.c: Indent labels correctly. * readelf.c: Likewise. * resres.c: Likewise. gas/ * config/obj-elf.c: Indent labels correctly. * config/obj-macho.c: Likewise. * config/tc-aarch64.c: Likewise. * config/tc-alpha.c: Likewise. * config/tc-arm.c: Likewise. * config/tc-cr16.c: Likewise. * config/tc-crx.c: Likewise. * config/tc-frv.c: Likewise. * config/tc-i386-intel.c: Likewise. * config/tc-i386.c: Likewise. * config/tc-ia64.c: Likewise. * config/tc-mn10200.c: Likewise. * config/tc-mn10300.c: Likewise. * config/tc-nds32.c: Likewise. * config/tc-riscv.c: Likewise. * config/tc-s12z.c: Likewise. * config/tc-xtensa.c: Likewise. * config/tc-z80.c: Likewise. * read.c: Likewise. * symbols.c: Likewise. * write.c: Likewise. ld/ * emultempl/cskyelf.em: Indent labels correctly. * ldfile.c: Likewise. * ldlang.c: Likewise. * plugin.c: Likewise. opcodes/ * aarch64-asm.c: Indent labels correctly. * aarch64-dis.c: Likewise. * aarch64-gen.c: Likewise. * aarch64-opc.c: Likewise. * alpha-dis.c: Likewise. * i386-dis.c: Likewise. * nds32-asm.c: Likewise. * nfp-dis.c: Likewise. * visium-dis.c: Likewise.
2020-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2019-12-16ubsan: aarch64: left shift of negative valueAlan Modra1-9/+6
* aarch64-dis.c (sign_extend): Return uint64_t. Rewrite without conditional. (aarch64_ext_imm): Avoid signed overflow.
2019-12-11aarch64 disassembler infinite loopAlan Modra1-0/+2
Assembling this to an object and trying to disassemble results in objdump -d looping forever. .inst 0x45205120 PR 25270 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return false when field is zero for sve_size_tsz_bhs.
2019-11-07[binutils][aarch64] Bfloat16 enablement [2/X]Matthew Malcomson1-0/+1
Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions) to binutils. This patch introduces the following BFloat16 instructions to the aarch64 backend: bfdot, bfmmla, bfcvt, bfcvtnt, bfmlal[t/b], bfcvtn2. Committed on behalf of Mihail Ionescu. gas/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (vectype_to_qualifier): Special case the S_2H operand qualifier. * doc/c-aarch64.texi: Document bf16 and bf16mmla4 extensions. * testsuite/gas/aarch64/bfloat16.d: New test. * testsuite/gas/aarch64/bfloat16.s: New test. * testsuite/gas/aarch64/illegal-bfloat16.d: New test. * testsuite/gas/aarch64/illegal-bfloat16.l: New test. * testsuite/gas/aarch64/illegal-bfloat16.s: New test. * testsuite/gas/aarch64/sve-bfloat-movprfx.s: New test. * testsuite/gas/aarch64/sve-bfloat-movprfx.d: New test. include/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_BFLOAT16): New feature macros. (AARCH64_ARCH_V8_6): Include BFloat16 feature macros. (enum aarch64_opnd_qualifier): Introduce new operand qualifier AARCH64_OPND_QLF_S_2H. (enum aarch64_insn_class): Introduce new class "bfloat16". (BFLOAT16_SVE_INSNC): New feature set for bfloat16 instructions to support the movprfx constraint. opcodes/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H in reglane special case. * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode): Account for new instructions. * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H in reglane special case. * aarch64-opc.c (struct operand_qualifier_data): Add data for new AARCH64_OPND_QLF_S_2H qualifier. * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2, QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers. (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve, aarch64_feature_bfloat16_bfmmla4): New feature sets. (BFLOAT_SVE, BFLOAT): New feature set macros. (BFLOAT_SVE_INSN, BFLOAT_BFMMLA4_INSN, BFLOAT_INSN): New macros to define BFloat16 instructions. (aarch64_opcode_table): Define new instructions bfdot, bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t] bfcvtn2, bfcvt. Regression tested on aarch64-elf. Is it ok for trunk? Regards, Mihail
2019-07-01[gas][aarch64][SVE2] Fix pmull{t,b} requirement on SVE2-AESMatthew Malcomson1-8/+5
I had mistakenly given all variants of the new SVE2 instructions pmull{t,b} a dependency on the feature +sve2-aes. Only the variant specifying .Q -> .D sizes should have that restriction. This patch fixes that mistake and updates the testsuite to have extra tests (matching the given set of tests per line in aarch64-tbl.h that the rest of the SVE2 tests follow). We also add a line in the documentation of the command line to clarify how to enable `pmull{t,b}` of this larger size. This is needed because all other instructions gated under the `sve2-aes` architecture extension are marked in the instruction documentation by an `HaveSVE2AES` check while pmull{t,b} is gated under the `HaveSVE2PMULL128` check. Regtested targeting aarch64-linux. gas/ChangeLog: 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com> * testsuite/gas/aarch64/illegal-sve2-aes.d: Update tests. * testsuite/gas/aarch64/illegal-sve2.l: Update tests. * doc/c-aarch64.texi: Add special note of pmull{t,b} instructions under the sve2-aes architecture extension. * testsuite/gas/aarch64/illegal-sve2.s: Add small size pmull{t,b} instructions. * testsuite/gas/aarch64/sve2.d: Add small size pmull{t,b} disassembly. * testsuite/gas/aarch64/sve2.s: Add small size pmull{t,b} instructions. include/ChangeLog: 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_insn_class): sve_size_013 renamed to sve_size_13. opcodes/ChangeLog: 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new sve_size_13 icode to account for variant behaviour of pmull{t,b}. * aarch64-dis-2.c: Regenerate. * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new sve_size_13 icode to account for variant behaviour of pmull{t,b}. * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier. (OP_SVE_VVV_Q_D): Add new qualifier. (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier. (struct aarch64_opcode): Split pmull{t,b} into those requiring AES and those not.
2019-05-09[binutils][aarch64] New sve_size_tsz_bhs iclass.Matthew Malcomson1-0/+11
Add sve_size_tsz_bhs iclass needed for sqxtnb and similar instructions. This iclass encodes one of three variants by the most significant bit set in a 3-bit value where only one bit may be set. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_tsz_bhs iclass. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle sve_size_tsz_bhs iclass encode. * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle sve_size_tsz_bhs iclass decode.
2019-05-09[binutils][aarch64] New sve_shift_tsz_bhsd iclass.Matthew Malcomson1-0/+11
This new iclass encodes the variant by which is the most significant bit used of bits 23-22:20-19, where those bits are usually part of a given constant operand. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_insn_class): Add sve_shift_tsz_bhsd iclass. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle sve_shift_tsz_bhsd iclass encode. * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle sve_shift_tsz_bhsd iclass decode.
2019-05-09[binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand.Matthew Malcomson1-0/+11
Include a new iclass to extract the variant from the most significant 3 bits of this operand. Instructions such as rshrnb include a constant shift amount as an operand, where the most significant three bits of this operand determine what size elements the instruction is operating on. The new SVE_SHRIMM_UNPRED_22 operand denotes this constant encoded in bits 22:20-19:18-16 while the new sve_shift_tsz_hsd iclass denotes that the SVE qualifier is encoded in bits 22:20-19. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (parse_operands): Handle new SVE_SHRIMM_UNPRED_22 operand. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New SVE_SHRIMM_UNPRED_22 operand. (enum aarch64_insn_class): Add sve_shift_tsz_hsd iclass. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-asm.c (aarch64_ins_sve_shrimm): (aarch64_encode_variant_using_iclass): Handle sve_shift_tsz_hsd iclass encode. * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle sve_shift_tsz_hsd iclass decode. * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking for SVE_SHRIMM_UNPRED_22. (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22. * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22 operand.
2019-05-09[binutils][aarch64] New sve_size_013 iclass.Matthew Malcomson1-0/+10
Add sve_size_013 instruction class This new iclass handles instructions such as pmullb whose size specifier can only be encoded as 0, 1, or 3. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_013 iclass. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle sve_size_013 iclass encode. * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle sve_size_013 iclass decode.
2019-05-09[binutils][aarch64] New sve_size_bh iclass.Matthew Malcomson1-0/+1
Add new iclass sve_size_bh to handle instructions that have two variants encoded with the SVE_sz field. This iclass behaves the same as the sve_size_sd iclass, but it has a nicer name for those instructions that choose between variants using the "B" and "H" size qualifiers. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_bh iclass. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle sve_size_bh iclass encode. * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle sve_size_bh iclass decode.
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