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path: root/opcodes/aarch64-dis.c
AgeCommit message (Expand)AuthorFilesLines
2023-03-30aarch64: Add the SME2 shift instructionsRichard Sandiford1-0/+17
2023-03-30aarch64: Add the SME2 saturating conversion instructionsRichard Sandiford1-0/+4
2023-03-30aarch64: Add the SME2 MLAL and MLSL instructionsRichard Sandiford1-2/+6
2023-03-30aarch64: Add the SME2 maximum/minimum instructionsRichard Sandiford1-0/+7
2023-03-30aarch64: Add the SME2 ADD and SUB instructionsRichard Sandiford1-0/+2
2023-03-30aarch64: Add the SME2 ZT0 instructionsRichard Sandiford1-0/+15
2023-03-30aarch64: Add the SME2 predicate-related instructionsRichard Sandiford1-4/+29
2023-03-30aarch64: Add the SME2 multivector LD1 and ST1 instructionsRichard Sandiford1-1/+20
2023-03-30aarch64: Add the SME2 MOVA instructionsRichard Sandiford1-1/+59
2023-03-30aarch64: Add a _10 suffix to FLD_imm3Richard Sandiford1-2/+2
2023-03-30aarch64: Add support for strided register listsRichard Sandiford1-0/+5
2023-03-30aarch64: Regularise FLD_* suffixesRichard Sandiford1-5/+5
2023-03-30aarch64: Try to report invalid variants against the closest matchRichard Sandiford1-1/+2
2023-03-30aarch64: Rename za_tile_vector to za_indexRichard Sandiford1-17/+17
2023-03-30aarch64: Make SME instructions use F_STRICTRichard Sandiford1-47/+46
2023-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2022-07-29libopcodes/aarch64: add support for disassembler stylingAndrew Burgess1-32/+215
2022-06-29opcodes/aarch64: split off creation of comment text in disassemblerAndrew Burgess1-2/+13
2022-01-02Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2021-12-03aarch64: Fix uninitialised memoryRichard Sandiford1-1/+1
2021-12-02aarch64: Enforce P/M/E order for MOPS instructionsRichard Sandiford1-4/+23
2021-12-02aarch64: Add support for +mopsRichard Sandiford1-0/+11
2021-11-25Fix building the AArch64 assembler and disassembler when assertions are disab...Nick Clifton1-16/+17
2021-11-17aarch64: [SME] SVE2 instructions added to support SMEPrzemyslaw Wirkus1-0/+43
2021-11-17aarch64: [SME] Add SME mode selection and state access instructionsPrzemyslaw Wirkus1-2/+36
2021-11-17aarch64: [SME] Add LD1x, ST1x, LDR and STR instructionsPrzemyslaw Wirkus1-0/+50
2021-11-17aarch64: [SME] Add MOV and MOVA instructionsPrzemyslaw Wirkus1-0/+58
2021-11-05Missing va_end in aarch64-dis.cAlan Modra1-0/+1
2021-03-31Use bool in opcodesAlan Modra1-212/+212
2021-03-31Remove bfd_stdint.hAlan Modra1-1/+1
2021-03-22Add startswith function and use it instead of CONST_STRNEQ.Martin Liska1-5/+5
2021-01-08Fix places in the AArch64 opcodes library code where a call to assert() has s...Nick Clifton1-1/+3
2021-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2020-10-28aarch64: Add DSB instruction Armv8.7-a variantPrzemyslaw Wirkus1-0/+15
2020-09-08aarch64: Add support for Armv8-R system registersAlex Coplan1-1/+1
2020-09-08aarch64: Add base support for Armv8-RAlex Coplan1-0/+33
2020-08-21Fix problems with the AArch64 linker exposed by testing it with sanitization ...Nick Clifton1-1/+9
2020-04-20[AArch64, Binutils] Add missing TSB instructionSudakshina Das1-0/+10
2020-02-26Indent labelsAlan Modra1-1/+1
2020-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2019-12-16ubsan: aarch64: left shift of negative valueAlan Modra1-9/+6
2019-12-11aarch64 disassembler infinite loopAlan Modra1-0/+2
2019-11-07[binutils][aarch64] Bfloat16 enablement [2/X]Matthew Malcomson1-0/+1
2019-07-01[gas][aarch64][SVE2] Fix pmull{t,b} requirement on SVE2-AESMatthew Malcomson1-8/+5
2019-05-09[binutils][aarch64] New sve_size_tsz_bhs iclass.Matthew Malcomson1-0/+11
2019-05-09[binutils][aarch64] New sve_shift_tsz_bhsd iclass.Matthew Malcomson1-0/+11
2019-05-09[binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand.Matthew Malcomson1-0/+11
2019-05-09[binutils][aarch64] New sve_size_013 iclass.Matthew Malcomson1-0/+10
2019-05-09[binutils][aarch64] New sve_size_bh iclass.Matthew Malcomson1-0/+1
2019-05-09[binutils][aarch64] New sve_size_sd2 iclass.Matthew Malcomson1-0/+4
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