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2019-05-09[binutils][aarch64] New sve_size_013 iclass.Matthew Malcomson1-0/+10
Add sve_size_013 instruction class This new iclass handles instructions such as pmullb whose size specifier can only be encoded as 0, 1, or 3. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_013 iclass. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle sve_size_013 iclass encode. * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle sve_size_013 iclass decode.
2019-05-09[binutils][aarch64] New sve_size_bh iclass.Matthew Malcomson1-0/+1
Add new iclass sve_size_bh to handle instructions that have two variants encoded with the SVE_sz field. This iclass behaves the same as the sve_size_sd iclass, but it has a nicer name for those instructions that choose between variants using the "B" and "H" size qualifiers. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_bh iclass. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle sve_size_bh iclass encode. * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle sve_size_bh iclass decode.
2019-05-09[binutils][aarch64] New sve_size_sd2 iclass.Matthew Malcomson1-0/+4
Define new sve_size_sd2 iclass to distinguish between the two variants of ldnt1sb and ldnt1sh. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_sd2 iclass. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle sve_size_sd2 iclass encode. * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle sve_size_sd2 iclass decode. * aarch64-opc.c (fields): Handle SVE_sz2 field. * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
2019-05-09[binutils][aarch64] New iclass sve_size_hsd2.Matthew Malcomson1-0/+7
Add "sve_size_hsd2" iclass decode that uses the new FLD_SVE_size field value to determine the variant of an instruction. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_hsd2 iclass. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle sve_size_hsd2 iclass encode. * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle sve_size_hsd2 iclass decode. * aarch64-opc.c (fields): Handle SVE_size field. * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
2019-03-25AArch64: Have -D override mapping symbol as documented.Tamar Christina1-1/+2
The documentation for -D says that on Arm platforms -D should disassemble data as instructions. "If the target is an ARM architecture this switch also has the effect of forcing the disassembler to decode pieces of data found in code sections as if they were instructions. " This makes it do as it says on the tincan so it's more consistent with aarch32. The usecase here is for baremetal developers who have created their instructions using .word directives instead if .insn. Though for Linux users I do find this behavior somewhat non-optimal. Perhaps there should be a new flag that just disassembles the values following the actual mapping symbol? binutils/ChangeLog: * testsuite/binutils-all/aarch64/in-order-all.d: New test. * testsuite/binutils-all/aarch64/out-of-order-all.d: New test. * testsuite/binutils-all/aarch64/out-of-order.d: opcodes/ChangeLog: * aarch64-dis.c (print_insn_aarch64): Implement override.
2019-03-25AArch64: Fix AArch64 disassembler mapping symbol searchTamar Christina1-6/+38
My previous patch for AArch64 was not enough to catch all the cases where disassembling an out-of-order section could go wrong. It had missed the case DATA sections could be incorrectly disassembled as TEXT. Out of order here refers to an object file where sections are not listed in a monotonic increasing VMA order. The ELF ABI for AArch64 [1] specifies the following for mapping symbols: 1) A text section must always have a corresponding mapping symbol at it's start. 2) Data sections do not require any mapping symbols. 3) The range of a mapping symbol extends from the address it starts on up to the next mapping symbol (exclusive) or section end (inclusive). However there is no defined order between a symbol and it's corresponding mapping symbol in the symbol table. This means that while in general we look up for a corresponding mapping symbol, we have to make at least one check of the symbol below the address being disassembled. When disassembling different PCs within the same section, the search for mapping symbol can be cached somewhat. We know that the mapping symbol corresponding to the current PC is either the previous one used, or one at the same address as the current PC. However this optimization and mapping symbol search must stop as soon as we reach the end or start of the section. Furthermore if we're only disassembling a part of a section, the search is a allowed to search further than the current chunk, but is not allowed to search past it (The mapping symbol if there, must be at the same address, so in practice we usually stop at PC+4). lastly, since only data sections don't require a mapping symbol the default mapping type should be DATA and not INSN as previously defined, however if the binary has had all its symbols stripped than this isn't very useful. To fix this we determine the default based on the section flags. This will allow the disassembler to be more useful on stripped binaries. If there is no section than we assume you to be disassembling INSN. [1] https://developer.arm.com/docs/ihi0056/latest/elf-for-the-arm-64-bit-architecture-aarch64-abi-2018q4#aaelf64-section4-5-4 binutils/ChangeLog: * testsuite/binutils-all/aarch64/in-order.d: New test. * testsuite/binutils-all/aarch64/out-of-order.d: Disassemble data as well. opcodes/ChangeLog: * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search order.
2019-03-25AArch64: Fix disassembler bug with out-of-order sectionsTamar Christina1-1/+6
The AArch64 disassembler has an optimization that it uses to reduce the amount it has to search for mapping symbols during disassembly. This optimization assumes that sections are listed in the section header in monotonic increasing VMAs. However this is not a requirement for the ELF specification. Because of this when such "out of order" sections occur the disassembler would pick the wrong mapping symbol to disassemble the section with. This fixes it by explicitly passing along the stop offset for the current disassembly glob and when this changes compared to the previous one we've seen the optimization won't be performed. In effect this restarts the search from a well defined starting point. Usually the symbol's address. The existing stop_vma can't be used for this as it is allowed to be unset and setting this unconditionally would change the semantics of this field. binutils/ChangeLog: * objdump.c (disassemble_bytes): Pass stop_offset. * testsuite/binutils-all/aarch64/out-of-order.T: New test. * testsuite/binutils-all/aarch64/out-of-order.d: New test. * testsuite/binutils-all/aarch64/out-of-order.s: New test. include/ChangeLog: * dis-asm.h (struct disassemble_info): Add stop_offset. opcodes/ChangeLog: * aarch64-dis.c (last_stop_offset): New. (print_insn_aarch64): Use stop_offset.
2019-01-25AArch64: Remove ldgv and stgv instructions from Armv8.5-A Memory Tagging ↵Sudi Das1-17/+0
Extension. This patch is part of a series of patches to introduce a few changes to the Armv8.5-A Memory Tagging Extension. This patch removes the LDGV and STGV instructions. These instructions needed special infrastructure to support [base]! style for addressing mode. That is also removed now. Committed on behalf of Sudakshina Das. *** gas/ChangeLog *** * config/tc-aarch64.c (parse_address_main): Remove support for [base]! address expression. (parse_operands): Remove support for AARCH64_OPND_ADDR_SIMPLE_2. (warn_unpredictable_ldst): Remove support for ldstgv_indexed. * testsuite/gas/aarch64/armv8_5-a-memtag.d: Remove tests for ldgv and stgv. * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. *** include/ChangeLog *** * opcode/aarch64.h (enum aarch64_opnd): Remove AARCH64_OPND_ADDR_SIMPLE_2. (enum aarch64_insn_class): Remove ldstgv_indexed. *** opcodes/ChangeLog *** * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove. * aarch64-asm.h (ins_addr_simple_2): Likeiwse. * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise. * aarch64-dis.h (ext_addr_simple_2): Likewise. * aarch64-opc.c (operand_general_constraint_met_p): Remove case for ldstgv_indexed. (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2. * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv. (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated.
2019-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2018-11-12[BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging ExtensionSudakshina Das1-0/+17
This patch is part of the patch series to add support for ARMv8.5-A Memory Tagging Extensions which is an optional extension to ARMv8.5-A and is enabled using the +memtag command line option. This patch add support to the Bulk Allocation Tag instructions from MTE. These are the following instructions added in this patch: - LDGV <Xt>, [<Xn|SP>]! - STGV <Xt>, [<Xn|SP>]! This needed a new kind of operand for the new addressing [<Xn|SP>]! since this has no offset and only takes a pre-indexed version. Hence AARCH64_OPND_ADDR_SIMPLE_2 and ldtdgv_indexed are introduced. (AARCH64_OPND_ADDR_SIMPLE fulfilled the no offset criteria but does not allow writeback). We also needed new encoding and decoding functions to be able to do the same. where <Xt> : Is the 64-bit destination GPR. <Xn|SP> : Is the 64-bit first source GPR or Stack pointer. *** include/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMPLE_2. (aarch64_insn_class): Add ldstgv_indexed. *** opcodes/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * aarch64-asm.c (aarch64_ins_addr_simple_2): New. * aarch64-asm.h (ins_addr_simple_2): Declare the above. * aarch64-dis.c (aarch64_ext_addr_simple_2): New. * aarch64-dis.h (ext_addr_simple_2): Declare the above. * aarch64-opc.c (operand_general_constraint_met_p): Add case for AARCH64_OPND_ADDR_SIMPLE_2 and ldstgv_indexed. (aarch64_print_operand): Add case for AARCH64_OPND_ADDR_SIMPLE_2. * aarch64-tbl.h (aarch64_opcode_table): Add stgv and ldgv. (AARCH64_OPERANDS): Define ADDR_SIMPLE_2. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. *** gas/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (parse_operands): Add switch case for AARCH64_OPND_ADDR_SIMPLE_2 and allow [base]! for it. (warn_unpredictable_ldst): Exempt ldstgv_indexed for ldgv. * testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for ldgv and stgv. * testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise.
2018-11-12[BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging ↵Sudakshina Das1-1/+2
Extension This patch is part of the patch series to add support for ARMv8.5-A Memory Tagging Extensions which is an optional extension to ARMv8.5-A and is enabled using the +memtag command line option. This patch add support to the Tag setting instructions from MTE which consists of the following instructions: - STG [<Xn|SP>, #<simm>] - STG [<Xn|SP>, #<simm>]! - STG [<Xn|SP>], #<simm> - STZG [<Xn|SP>, #<simm>] - STZG [<Xn|SP>, #<simm>]! - STZG [<Xn|SP>], #<simm> - ST2G [<Xn|SP>, #<simm>] - ST2G [<Xn|SP>, #<simm>]! - ST2G [<Xn|SP>], #<simm> - STZ2G [<Xn|SP>, #<simm>] - STZ2G [<Xn|SP>, #<simm>]! - STZ2G [<Xn|SP>], #<simm> - STGP <Xt>, <Xt2>, [<Xn|SP>, #<imm>] - STGP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]! - STGP <Xt>, <Xt2>, [<Xn|SP>], #<imm> where <Xn|SP> : Is the 64-bit GPR or Stack pointer. <simm> : Is the optional signed immediate offset, a multiple of 16 in the range -4096 to 4080, defaulting to 0. *** include/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13. (aarch64_opnd_qualifier): Add new AARCH64_OPND_QLF_imm_tag. *** opcodes/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * aarch64-opc.c (aarch64_opnd_qualifiers): Add new data for AARCH64_OPND_QLF_imm_tag. (operand_general_constraint_met_p): Add case for AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13. (aarch64_print_operand): Likewise. * aarch64-tbl.h (QL_LDST_AT, QL_STGP): New. (aarch64_opcode_table): Add stg, stzg, st2g, stz2g and stgp for both offset and pre/post indexed versions. (AARCH64_OPERANDS): Define ADDR_SIMM11 and ADDR_SIMM13. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. *** gas/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (parse_operands): Add switch case for AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13. (fix_insn): Likewise. (warn_unpredictable_ldst): Exempt STGP. * testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for stg, st2g, stzg, stz2g and stgp. * testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise.
2018-11-12[BINUTILS, AARCH64, 2/8] Add Tag generation instructions in Memory Tagging ↵Sudakshina Das1-0/+2
Extension This patch is part of the patch series to add support for ARMv8.5-A Memory Tagging Extensions which is an optional extension to ARMv8.5-A and is enabled using the +memtag command line option. This patch add support to the Tag generation instructions from MTE. These are the following instructions added in this patch: - IRG <Xd|SP>, <Xn|SP>{, Xm} - ADDG <Xd|SP>, <Xn|SP>, #<uimm1>. #<uimm2> - SUBG <Xd|SP>, <Xn|SP>, #<uimm1>. #<uimm2> - GMI <Xd>, <Xn|SP>, <Xm> where <Xd|SP> : Is the 64-bit destination GPR or Stack pointer. <Xn|SP> : Is the 64-bit source GPR or Stack pointer. <uimm6> : Is the unsigned immediate, a multiple of 16 in the range 0 to 1008. <uimm4> : Is the unsigned immediate, in the range 0 to 15. *** include/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10 as new enums. *** opcodes/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * aarch64-opc.h (aarch64_field_kind): New FLD_imm4_3. (OPD_F_SHIFT_BY_4, operand_need_shift_by_four): New. * aarch64-opc.c (fields): Add entry for imm4_3. (operand_general_constraint_met_p): Add cases for AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10. (aarch64_print_operand): Likewise. * aarch64-tbl.h (QL_ADDG): New. (aarch64_opcode_table): Add addg, subg, irg and gmi. (AARCH64_OPERANDS): Define UIMM4_ADDG and UIMM10. * aarch64-asm.c (aarch64_ins_imm): Add case for operand_need_shift_by_four. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. *** gas/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (parse_operands): Add switch case for AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10. * testsuite/gas/aarch64/armv8_5-a-memtag.s: New. * testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise. * testsuite/gas/aarch64/illegal-memtag.d: Likewise.
2018-10-09[PATCH, BINUTILS, AARCH64, 7/9] Add BTI instructionSudakshina Das1-1/+1
This patch is part of the patch series to add support for ARMv8.5-A extensions. (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order/bti-branch-target-identification) The Branch Target Identification instructions (BTI) are allocated to existing HINT space, using HINT numbers 32, 34, 36, 38, such that bits[7:6] of the instruction identify the compatibility of the BTI instruction to different branches. BTI {<targets>} where <targets> one of the following, specifying which type of indirection is allowed: j : Can be a target of any BR Xn isntruction. c : Can be a target of any BLR Xn and BR {X16|X17}. jc: Can be a target of any free branch. A BTI instruction without any <targets> is the strictest of all and can not be a target of nay free branch. *** include/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_BTI): New. (AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_BTI by default. (aarch64_opnd): Add AARCH64_OPND_BTI_TARGET. (HINT_OPD_CSYNC, HINT_OPD_C, HINT_OPD_J): New macros to define HINT #imm values. (HINT_OPD_JC, HINT_OPD_NULL): Likewise. *** opcodes/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New. (HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag with the hint immediate. * aarch64-opc.c (aarch64_hint_options): New entries for c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI. (aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET while checking for HINT_OPD_F_NOPRINT flag. * aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to extract value. * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New. (aarch64_opcode_table): Add entry for BTI. (AARCH64_OPERANDS): Add new description for BTI targets. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. *** gas/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (parse_bti_operand): New. (process_omitted_operand): Add case for AARCH64_OPND_BTI_TARGET. (parse_operands): Likewise. * testsuite/gas/aarch64/system.d: Update for BTI. * testsuite/gas/aarch64/bti.s: New. * testsuite/gas/aarch64/bti.d: New. * testsuite/gas/aarch64/illegal-bti.d: New. * testsuite/gas/aarch64/illegal-bti.l: New.
2018-10-09[PATCH, BINUTILS, AARCH64, 4/9] Add Execution and Data Restriction instructionsSudakshina Das1-0/+6
This patch is part of the patch series to add support for ARMv8.5-A extensions. (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order) This patch adds the prediction restriction instructions (that is, cfp, dvp, cpp). These instructions are retrospectively made optional for all versions of the architecture from ARMv8.0 to ARMv8.4 and is mandatory from ARMv8.5. Hence adding a new +predres which can be used by the older architectures. *** include/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_PREDRES): New. (AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_PREDRES by default. (aarch64_opnd): Add AARCH64_OPND_SYSREG_SR. (aarch64_sys_regs_sr): Declare new table. *** opcodes/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * aarch64-dis.c (aarch64_ext_sysins_op): Add case for AARCH64_OPND_SYSREG_SR. * aarch64-opc.c (aarch64_print_operand): Likewise. (aarch64_sys_regs_sr): Define table. (aarch64_sys_ins_reg_supported_p): Check for RCTX with AARCH64_FEATURE_PREDRES. * aarch64-tbl.h (aarch64_feature_predres): New. (PREDRES, PREDRES_INSN): New. (aarch64_opcode_table): Add entries for cfp, dvp and cpp. (AARCH64_OPERANDS): Add new description for SYSREG_SR. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. *** gas/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (aarch64_sys_regs_sr_hsh): New. (parse_operands): Add entry for AARCH64_OPND_SYSREG_SR. (md_begin): Allocate and initialize aarch64_sys_regs_sr_hsh with aarch64_sys_regs_sr. (aarch64_features): Add new "predres" option for older architectures. * doc/c-aarch64.texi: Document the same. * testsuite/gas/aarch64/sysreg-4.s: New. * testsuite/gas/aarch64/sysreg-4.d: New. * testsuite/gas/aarch64/illegal-sysreg-4.d: New. * testsuite/gas/aarch64/illegal-sysreg-4.l: New. * testsuite/gas/aarch64/predres.s: New. * testsuite/gas/aarch64/predres.d: New.
2018-10-03AArch64: Constraint disassembler and assembler changes.Tamar Christina1-7/+59
This patch wires in the new constraint verifiers into the assembler and disassembler. Because of this the MOVPRFX tests have to be split out from the generic SVE tests into their own tests so warnings can be ignored. These tests are only intended to test the encoding correctness and not the constraints. gas/ * testsuite/gas/aarch64/sve-movprfx.d: New test. * testsuite/gas/aarch64/sve-movprfx.s: New test. * testsuite/gas/aarch64/sve.d: Refactor. * testsuite/gas/aarch64/sve.s: Refactor. * testsuite/gas/aarch64/sysreg-diagnostic.d: Update. opcodes/ * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier. * aarch64-dis.c (print_operands): Refactor to take notes. (print_verifier_notes): New. (print_aarch64_insn): Apply constraint verifier. (print_insn_aarch64_word): Update call to print_aarch64_insn. * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
2018-10-03AArch64: Refactor verifiers to make more general.Tamar Christina1-1/+2
The current verifiers only take an instruction description and encoded value as arguments. This was enough when the verifiers only needed to do simple checking but it's insufficient for the purposes of validating instruction sequences. This patch adds the required arguments and also a flag to allow a verifier to distinguish between whether it's being run during encoding or decoding. It also allows for errors and warnings to be returned by a verifier instead of a simple pass/fail. include/ * opcode/aarch64.h (struct aarch64_opcode): Expand verifiers to take more arguments. opcodes/ * aarch64-dis.c (aarch64_opcode_decode): Update verifier call. * aarch64-opc.c (verify_ldpsw): Update arguments.
2018-10-03AArch64: Refactor err_type.Tamar Christina1-13/+8
Previously the ERR_ values were defined as different constants, to make this a bit more type safe and so they can be more easily re-used I'm changing them into an actual enum and updating any usages. include/ * opcode/aarch64.h (enum err_type): New. (aarch64_decode_insn): Use it. opcodes/ * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove. (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
2018-10-03AArch64: Wire through instr_sequenceTamar Christina1-0/+3
This patch introduces aarch64_instr_sequence which is a structure similar to IT blocks on Arm in order to track instructions that introduce a constraint or dependency on instruction 1..N positions away from the instruction that opened the block. The struct is also wired through to the locations that require it. gas/ * config/tc-aarch64.c (now_instr_sequence): (*insn_sequence, now_instr_sequence): New. (output_operand_error_record, do_encode): Add insn_sequence. (md_assemble): Update insn_sequence. (try_to_encode_as_unscaled_ldst, fix_mov_imm_insn, fix_insn): Pass insn_sequence. * config/tc-aarch64.h (struct aarch64_segment_info_type): Add insn_sequence. include/ * opcode/aarch64.h (struct aarch64_instr_sequence): New. (aarch64_opcode_encode): Use it. opcodes/ * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence. * aarch64-dis.c (insn_sequence): New.
2018-06-29Fix AArch64 encodings for by element instructions.Tamar Christina1-5/+14
Some instructions in Armv8-a place a limitation on FP16 registers that can be used as the register from which to select an element from. e.g. fmla restricts Rm to 4 bits when using an FP16 register. This restriction does not apply for all instructions, e.g. fcmla does not have this restriction as it gets an extra bit from the M field. Unfortunately, this restriction to S_H was added for all _Em operands before, meaning for a large number of instructions you couldn't use the full register file. This fixes the issue by introducing a new operand _Em16 which applies this restriction only when paired with S_H and leaves the _Em and the other qualifiers for _Em16 unbounded (i.e. using the full 5 bit range). Also the patch updates all instructions that should be affected by this. opcodes/ PR binutils/23192 * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint. * aarch64-opc.c (operand_general_constraint_met_p, aarch64_print_operand): Likewise. * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal, smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl, fmlal2, fmlsl2. (AARCH64_OPERANDS): Add Em2. gas/ PR binutils/23192 * config/tc-aarch64.c (process_omitted_operand, parse_operands): Add AARCH64_OPND_Em16 * testsuite/gas/aarch64/advsimd-armv8_3.s: Expand tests to cover upper 16 registers. * testsuite/gas/aarch64/advsimd-armv8_3.d: Likewise. * testsuite/gas/aarch64/advsimd-compnum.s: Likewise. * testsuite/gas/aarch64/advsimd-compnum.d: Likewise. * testsuite/gas/aarch64/sve.d: Likewise. include/ PR binutils/23192 *opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_Em16.
2018-05-15Implement Read/Write constraints on system registers on AArch64Tamar Christina1-1/+16
This patch adds constraints for read and write only system registers with the msr and mrs instructions. The code will treat having both flags set and none set as the same. These flags add constraints that must be matched up. e.g. a system register with a READ only flag set, can only be used with mrs. If The constraint fails a warning is emitted. Examples of the warnings generated: test.s: Assembler messages: test.s:5: Warning: specified register cannot be written to at operand 1 -- `msr dbgdtrrx_el0,x3' test.s:7: Warning: specified register cannot be read from at operand 2 -- `mrs x3,dbgdtrtx_el0' test.s:8: Warning: specified register cannot be written to at operand 1 -- `msr midr_el1,x3' and disassembly notes: 0000000000000000 <main>: 0: d5130503 msr dbgdtrtx_el0, x3 4: d5130503 msr dbgdtrtx_el0, x3 8: d5330503 mrs x3, dbgdtrrx_el0 c: d5330503 mrs x3, dbgdtrrx_el0 10: d5180003 msr midr_el1, x3 ; note: writing to a read-only register. Note that because dbgdtrrx_el0 and dbgdtrtx_el0 have the same encoding, during disassembly the constraints are use to disambiguate between the two. An exact constraint match is always prefered over partial ones if available. As always the warnings can be suppressed with -w and also be made errors using warnings as errors. binutils/ PR binutils/21446 * doc/binutils.texi (-M): Document AArch64 options. gas/ PR binutils/21446 * testsuite/gas/aarch64/illegal-sysreg-2.s: Fix pmbidr_el1 test. * testsuite/gas/aarch64/illegal-sysreg-2.l: Likewise. * testsuite/gas/aarch64/illegal-sysreg-2.d: Likewise. * testsuite/gas/aarch64/sysreg-diagnostic.s: New. * testsuite/gas/aarch64/sysreg-diagnostic.l: New. * testsuite/gas/aarch64/sysreg-diagnostic.d: New. include/ PR binutils/21446 * opcode/aarch64.h (F_SYS_READ, F_SYS_WRITE): New. opcodes/ PR binutils/21446 * aarch64-asm.c (opintl.h): Include. (aarch64_ins_sysreg): Enforce read/write constraints. * aarch64-dis.c (aarch64_ext_sysreg): Likewise. * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here. (F_REG_READ, F_REG_WRITE): New. * aarch64-opc.c (aarch64_print_operand): Generate notes for AARCH64_OPND_SYSREG. (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h. (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0, mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1, id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1, id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1, id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1, mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1, id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1, id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1, id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1, csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2, rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0, mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1, mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1, pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0. * aarch64-tbl.h (aarch64_opcode_table): Add constraints to msr (F_SYS_WRITE), mrs (F_SYS_READ).
2018-05-15Allow non-fatal errors to be emitted and for disassembly notes be placed on ↵Tamar Christina1-2/+25
AArch64 This patch adds a new platform option "notes" that can be used to indicate if disassembly notes should be placed in the disassembly as comments. These notes can contain information about a failing constraint such as reading from a write-only register. The disassembly will not be blocked because of this but -M notes will emit a comment saying that the operation is not allowed. For assembly this patch adds a new non-fatal status for errors. This is essentially a warning. The reason for not creating an actual warning type is that this causes the interaction between the ordering of warnings and errors to be problematic. Currently the error buffer is almost always filled because of the way operands are matched during assembly. An earlier template may have put an error there that would only be displayed if no other template matches or generates a higher priority error. But by definition a warning is lower priority than a warning, so the error (which is incorrect if another template matched) will supersede the warning. By treating warnings as errors and only later relaxing the severity this relationship keeps working and the existing reporting infrastructure can be re-used. binutils/ PR binutils/21446 * doc/binutils.texi (-M): Document AArch64 options. * NEWS: Document notes and warnings. gas/ PR binutils/21446 * config/tc-aarch64.c (print_operands): Indicate no notes. (output_operand_error_record): Support non-fatal errors. (output_operand_error_report, warn_unpredictable_ldst, md_assemble): Likewise. include/ PR binutils/21446 * opcode/aarch64.h (aarch64_operand_error): Add non_fatal. (aarch64_print_operand): Support notes. opcodes/ PR binutils/21446 * aarch64-dis.c (no_notes: New. (parse_aarch64_dis_option): Support notes. (aarch64_decode_insn, print_operands): Likewise. (print_aarch64_disassembler_options): Document notes. * aarch64-opc.c (aarch64_print_operand): Support notes.
2018-05-15Modify AArch64 Assembly and disassembly functions to be able to fail and ↵Tamar Christina1-233/+299
report why. This patch if the first patch in a series to add the ability to add constraints to system registers that an instruction must adhere to in order for the register to be usable with that instruction. These constraints can also be used to disambiguate between registers with the same encoding during disassembly. This patch adds a new flags entry in the sysreg structures and ensures it is filled in and read out during assembly/disassembly. It also adds the ability for the assemble and disassemble functions to be able to gracefully fail and re-use the existing error reporting infrastructure. The return type of these functions are changed to a boolean to denote success or failure and the error structure is passed around to them. This requires aarch64-gen changes so a lot of the changes here are just mechanical. gas/ PR binutils/21446 * config/tc-aarch64.c (parse_sys_reg): Return register flags. (parse_operands): Fill in register flags. gdb/ PR binutils/21446 * aarch64-tdep.c (aarch64_analyze_prologue, aarch64_software_single_step, aarch64_displaced_step_copy_insn): Indicate not interested in errors. include/ PR binutils/21446 * opcode/aarch64.h (aarch64_opnd_info): Change sysreg to struct. (aarch64_decode_insn): Accept error struct. opcodes/ PR binutils/21446 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean and take error struct. * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane, aarch64_ins_reglist, aarch64_ins_ldst_reglist, aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist, aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half, aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm, aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits, aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm, aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple, aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm, aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12, aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg, aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier, aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended, aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl, aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl, aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6, aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw, aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz, aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw, aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm, aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov, aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist, aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm, aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two, aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise. * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise. * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane, aarch64_ext_reglist, aarch64_ext_ldst_reglist, aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist, aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half, aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm, aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits, aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm, aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple, aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm, aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12, aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg, aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier, aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended, aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl, aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl, aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6, aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw, aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz, aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw, aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm, aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov, aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist, aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm, aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two, aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise. (determine_disassembling_preference, aarch64_decode_insn, print_insn_aarch64_word, print_insn_data): Take errors struct. (print_insn_aarch64): Use errors. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-gen.c (print_operand_inserter): Use errors and change type to boolean in aarch64_insert_operan. (print_operand_extractor): Likewise. * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
2018-05-01Fix unintialized memory in aarch64 opcodes.Tamar Christina1-3/+3
This patch fixes an issue where the memory for the opcode structure is not zero'd before the first exit branch. So there is one failure mode for which uninitialized memory is returned. This causes weird failures when the return code is not checked before inst is used. opcodes/ * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
2018-03-03opcodes error messagesAlan Modra1-1/+1
Another patch aimed at making binutils comply with the GNU coding standard. The generated files require https://sourceware.org/ml/cgen/2018-q1/msg00004.html cpu/ * frv.opc: Include opintl.h. (add_next_to_vliw): Use opcodes_error_handler to print error. Standardize error message. (fr500_check_insn_major_constraints, frv_vliw_add_insn): Likewise. opcodes/ * sysdep.h (opcodes_error_handler): Define. (_bfd_error_handler): Declare. * Makefile.am: Remove stray #. * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT EDIT" comment. * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c, * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c, * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use opcodes_error_handler to print errors. Standardize error messages. * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise, and include opintl.h. * nds32-asm.c: Likewise, and include sysdep.h and opintl.h. * i386-gen.c: Standardize error messages. * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate. * Makefile.in: Regenerate. * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c, * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c, * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c, * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c, * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c, * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c, * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c, * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c, * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c, * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c, * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c, * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2018-01-03Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2017-12-19Correct disassembly of dot product instructions.Tamar Christina1-1/+1
Dot products deviate from the normal disassembly rules for lane indexed instruction. Their canonical representation is in the form of: v0.2s, v0.8b, v0.4b[0] instead of v0.2s, v0.8b, v0.b[0] to try to denote that these instructions select 4x 1 byte elements instead of a single 1 byte element. Previously we were disassembling them following the normal rules, this patch corrects the disassembly. gas/ PR gas/22559 * config/tc-aarch64.c (vectype_to_qualifier): Support AARCH64_OPND_QLF_S_4B. * gas/testsuite/gas/aarch64/dotproduct.d: Update disassembly. include/ PR gas/22559 * aarch64.h (aarch64_opnd_qualifier): Add AARCH64_OPND_QLF_S_4B. opcodes/ PR gas/22559 * aarch64-asm.c (aarch64_ins_reglane): Change AARCH64_OPND_QLF_S_B to AARCH64_OPND_QLF_S_4B * aarch64-dis.c (aarch64_ext_reglane): Change AARCH64_OPND_QLF_S_B to AARCH64_OPND_QLF_S_4B * aarch64-opc.c (aarch64_opnd_qualifiers): Add 4b variant. * aarch64-tbl.h (QL_V2DOT): Change S_B to S_4B.
2017-12-11[Binutils][Objdump]Check symbol section information while search a mapping ↵Renlin Li1-3/+5
symbol backward. When checking mapping symbols backwardly, the section which defines the symbol is not considerted. This patch fixes this by moving the section checking code into get_sym_code_type () function which is shared by forward and backword mapping symbol searching. opcodes/ 2017-12-11 Petr Pavlu <petr.pavlu@arm.com> Renlin Li <renlin.li@arm.com> * aarch64-dis.c (print_insn_aarch64): Move symbol section check ... (get_sym_code_type): Here. binutils/ 2017-12-11 Renlin Li <renlin.li@arm.com> * testsuite/binutils-all/aarch64/objdump.d: New. * testsuite/binutils-all/aarch64/objdump.s: New.
2017-11-09Adds the new Fields and Operand types for the new instructions in Armv8.4-a.Tamar Christina1-0/+27
gas/ * config/tc-aarch64.c (process_omitted_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2 and AARCH64_OPND_IMM_2. (parse_operands): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2, AARCH64_OPND_IMM_2, AARCH64_OPND_MASK and AARCH64_OPND_ADDR_OFFSET. include/ * opcode/aarch64.h: (aarch64_opnd): Add AARCH64_OPND_Va, AARCH64_OPND_MASK, AARCH64_OPND_IMM_2, AARCH64_OPND_ADDR_OFFSET and AARCH64_OPND_SM3_IMM2. (aarch64_insn_class): Add cryptosm3 and cryptosm4. (arch64_feature_set): Make uint64_t. opcodes/ * aarch64-asm.h (ins_addr_offset): New. * aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3. (aarch64_ins_addr_offset): New. * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_addr_offset): New. * aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3. (aarch64_ext_addr_offset): New. * aarch64-dis-2.c: Regenerate. * aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2, FLD_imm4_2 and FLD_SM3_imm2. * aarch64-opc.c (fields): Add FLD_imm6_2, FLD_imm4_2 and FLD_SM3_imm2. (operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET. (aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2, AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET. * aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New. * aarch64-tbl.h (aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
2017-06-28[AArch64] Add dot product support for AArch64 to binutilsTamar Christina1-0/+15
gas/ * config/tc-aarch64.c (aarch64_reg_parse_32_64): Accept 4B. (aarch64_features): Added dotprod. * doc/c-aarch64.texi: Added dotprod. * testsuite/gas/aarch64/dotproduct.d: New. * testsuite/gas/aarch64/dotproduct.s: New. opcodes/ * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod. * aarch64-dis.c (aarch64_ext_reglane): Likewise. * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New. (aarch64_feature_dotprod, DOT_INSN): New. (udot, sdot): New. * aarch64-dis-2.c: Regenerated. include/ * opcode/aarch64.h: (AARCH64_FEATURE_DOTPROD): New. (aarch64_insn_class): Added dotprod.
2017-06-15Prevent address violation problem when disassembling corrupt aarch64 binary.Nick Clifton1-0/+3
PR binutils/21595 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of range value.
2017-06-14Don't use print_insn_XXX in GDBYao Qi1-1/+1
This is a follow-up to [PATCH 0/6] Unify the disassembler selection in gdb and objdump https://sourceware.org/ml/binutils/2017-05/msg00192.html that is, opcodes is able to select the right disassembler, so gdb doesn't have to select them. Instead, gdb can just use default_print_insn. As a result, these print_insn_XXX are not used out of opcodes, so this patch also moves their declarations from include/dis-asm.h to opcodes/disassemble.h. With this change, GDB doesn't use any print_insn_XXX directly any more. gdb: 2017-06-14 Yao Qi <yao.qi@linaro.org> * aarch64-tdep.c (aarch64_gdb_print_insn): Call default_print_insn instead of print_insn_aarch64. * arm-tdep.c (gdb_print_insn_arm): Call default_print_insn instead of print_insn_big_arm and print_insn_little_arm. * i386-tdep.c (i386_print_insn): Call default_print_insn instead of print_insn_i386. * ia64-tdep.c (ia64_print_insn): Call default_print_insn instead of print_insn_ia64. * mips-tdep.c (gdb_print_insn_mips): Call default_print_insn instead of print_insn_big_mips and print_insn_little_mips. * spu-tdep.c (gdb_print_insn_spu): Call default_print_insn instead of print_insn_spu. include: 2017-06-14 Yao Qi <yao.qi@linaro.org> * dis-asm.h (print_insn_aarch64): Move it to opcodes/disassemble.h. (print_insn_big_arm, print_insn_big_mips): Likewise. (print_insn_i386, print_insn_ia64): Likewise. (print_insn_little_arm, print_insn_little_mips): Likewise. (print_insn_spu): Likewise. opcodes: 2017-06-14 Yao Qi <yao.qi@linaro.org> * aarch64-dis.c: Include disassemble.h instead of dis-asm.h. * arm-dis.c: Likewise. * ia64-dis.c: Likewise. * mips-dis.c: Likewise. * spu-dis.c: Likewise. * disassemble.h (print_insn_aarch64): New declaration, moved from include/dis-asm.h. (print_insn_big_arm, print_insn_big_mips): Likewise. (print_insn_i386, print_insn_ia64): Likewise. (print_insn_little_arm, print_insn_little_mips): Likewise.
2017-05-18Don't compare boolean values against TRUE or FALSEAlan Modra1-4/+4
bfd/ * arc-got.h: Don't compare boolean values against TRUE or FALSE. * elf-m10300.c: Likewise. * elf.c: Likewise. * elf32-arc.c: Likewise. * elf32-bfin.c: Likewise. * elf32-m68k.c: Likewise. * elf32-nds32.c: Likewise. * elf32-tilepro.c: Likewise. * elflink.c: Likewise. * elfnn-aarch64.c: Likewise. * elfnn-riscv.c: Likewise. * elfxx-tilegx.c: Likewise. * mach-o.c: Likewise. * peXXigen.c: Likewise. * vms-alpha.c: Likewise. * vms-lib.c: Likewise. opcodes/ * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE. * aarch64-dis.c: Likewise. * aarch64-gen.c: Likewise. * aarch64-opc.c: Likewise. binutils/ * strings.c: Don't compare boolean values against TRUE or FALSE. gas/ * config/tc-aarch64.c: Don't compare booleans against TRUE or FALSE. * config/tc-hppa.c: Likewise. * config/tc-mips.c: Likewise. * config/tc-score7.c: Likewise. ld/ * emultempl/elf32.em: Don't compare boolean values against TRUE or FALSE. * emultempl/pe.em: Likewise. * emultempl/pep.em: Likewise. * emultempl/xtensaelf.em: Likewise.
2017-02-24[AArch64] Additional SVE instructionsRichard Sandiford1-31/+48
This patch supports some additions to the SVE architecture prior to its public release. include/ * opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4x16) (AARCH64_OPND_SVE_IMM_ROT1, AARCH64_OPND_SVE_IMM_ROT2) (AARCH64_OPND_SVE_Zm3_INDEX, AARCH64_OPND_SVE_Zm3_22_INDEX) (AARCH64_OPND_SVE_Zm4_INDEX): New aarch64_opnds. opcodes/ * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD) (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD) (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S) (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H) (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH) (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD) (OP_SVE_V_HSD): New macros. (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD) (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD) (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete. (aarch64_opcode_table): Add new SVE instructions. (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate for rotation operands. Add new SVE operands. * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter. (ins_sve_quad_index): Likewise. (ins_imm_rotate): Split into... (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters. * aarch64-asm.c (aarch64_ins_imm_rotate): Split into... (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two functions. (aarch64_ins_sve_addr_ri_s4): New function. (aarch64_ins_sve_quad_index): Likewise. (do_misc_encoding): Handle "MOV Zn.Q, Qm". * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor. (ext_sve_quad_index): Likewise. (ext_imm_rotate): Split into... (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors. * aarch64-dis.c (aarch64_ext_imm_rotate): Split into... (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two functions. (aarch64_ext_sve_addr_ri_s4): New function. (aarch64_ext_sve_quad_index): Likewise. (aarch64_ext_sve_index): Allow quad indices. (do_misc_decoding): Likewise. * aarch64-dis-2.c: Regenerate. * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New aarch64_field_kinds. (OPD_F_OD_MASK): Widen by one bit. (OPD_F_NO_ZR): Bump accordingly. (get_operand_field_width): New function. * aarch64-opc.c (fields): Add new SVE fields. (operand_general_constraint_met_p): Handle new SVE operands. (aarch64_print_operand): Likewise. * aarch64-opc-2.c: Regenerate. gas/ * doc/c-aarch64.texi: Document that sve implies fp16, simd and compnum. * config/tc-aarch64.c (parse_vector_type_for_operand): Allow .q to be used with SVE registers. (parse_operands): Handle new SVE operands. (aarch64_features): Make "sve" require F16 rather than FP. Also require COMPNUM. * testsuite/gas/aarch64/sve.s: Add tests for new instructions. Include compnum tests. * testsuite/gas/aarch64/sve.d: Update accordingly. * testsuite/gas/aarch64/sve-invalid.s: Add tests for new instructions. * testsuite/gas/aarch64/sve-invalid.l: Update accordingly. Also update expected output for new FMOV and MOV alternatives.
2017-01-02Update year range in copyright notice of all files.Alan Modra1-1/+1
2016-11-18[AArch64] Add ARMv8.3 FCMLA and FCADD instructionsSzabolcs Nagy1-0/+42
Add support for FCMLA and FCADD complex arithmetic SIMD instructions. FCMLA has an indexed element variant where the index range has to be treated specially because a complex number takes two elements and the indexed vector size depends on the other operands. These complex number SIMD instructions are part of ARMv8.3 https://community.arm.com/groups/processors/blog/2016/10/27/armv8-a-architecture-2016-additions include/ 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com> * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_IMM_ROT1, AARCH64_OPND_IMM_ROT2, AARCH64_OPND_IMM_ROT3. (enum aarch64_op): Add OP_FCMLA_ELEM. opcodes/ 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com> * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define. (aarch64_feature_simd_v8_3, SIMD_V8_3): Define. (aarch64_opcode_table): Add fcmla and fcadd. (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}. * aarch64-asm.h (aarch64_ins_imm_rotate): Declare. * aarch64-asm.c (aarch64_ins_imm_rotate): Define. * aarch64-dis.h (aarch64_ext_imm_rotate): Declare. * aarch64-dis.c (aarch64_ext_imm_rotate): Define. * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}. * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}. (operand_general_constraint_met_p): Rotate and index range check. (aarch64_print_operand): Handle rotate operand. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. gas/ 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com> * config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_IMM_ROT*. * testsuite/gas/aarch64/advsimd-armv8_3.d: New. * testsuite/gas/aarch64/advsimd-armv8_3.s: New. * testsuite/gas/aarch64/illegal-fcmla.s: New. * testsuite/gas/aarch64/illegal-fcmla.l: New. * testsuite/gas/aarch64/illegal-fcmla.d: New.
2016-11-18[AArch64] Add ARMv8.3 combined pointer authentication load instructionsSzabolcs Nagy1-0/+21
Add support for ARMv8.3 LDRAA and LDRAB combined pointer authentication and load instructions. These instructions authenticate the base register and load 8 byte from it plus a scaled 10-bit offset with optional writeback to update the base register. A new instruction class (ldst_imm10) and operand type (AARCH64_OPND_ADDR_SIMM10) were introduced to handle the special addressing form. include/ 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com> * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM10. (enum aarch64_insn_class): Add ldst_imm10. opcodes/ 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com> * aarch64-tbl.h (QL_X1NIL): New. (arch64_opcode_table): Add ldraa, ldrab. (AARCH64_OPERANDS): Add "ADDR_SIMM10". * aarch64-asm.h (aarch64_ins_addr_simm10): Declare. * aarch64-asm.c (aarch64_ins_addr_simm10): Define. * aarch64-dis.h (aarch64_ext_addr_simm10): Declare. * aarch64-dis.c (aarch64_ext_addr_simm10): Define. * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10. * aarch64-opc.c (fields): Add data for FLD_S_simm10. (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10. (aarch64_print_operand): Likewise. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. gas/ 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com> * config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_ADDR_SIMM10. (fix_insn): Likewise. (warn_unpredictable_ldst): Handle ldst_imm10. * testsuite/gas/aarch64/pac.s: Add ldraa and ldrab tests. * testsuite/gas/aarch64/pac.d: Likewise. * testsuite/gas/aarch64/illegal-ldraa.s: New. * testsuite/gas/aarch64/illegal-ldraa.l: New. * testsuite/gas/aarch64/illegal-ldraa.d: New.
2016-10-18AArch64/opcodes: Correct an `index' global shadowing errorMaciej W. Rozycki1-4/+4
Fix a commit 4df068de5214 ("Add support for SVE addressing modes") build regression: cc1: warnings being treated as errors .../opcodes/aarch64-dis.c: In function 'aarch64_ext_sve_addr_rr_lsl': .../opcodes/aarch64-dis.c:1324: error: declaration of 'index' shadows a global declaration /usr/include/string.h:303: error: shadowed declaration is here make[3]: *** [aarch64-dis.lo] Error 1 in a way following commit 91d6fa6a035c ("Add -Wshadow to the gcc command line options used when compiling the binutils."). opcodes/ * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index' local variable to `index_regno'.
2016-10-06-Wimplicit-fallthrough warning fixesAlan Modra1-0/+5
Comment changes. bfd/ * coff-h8300.c: Spell fall through comments consistently. * coffgen.c: Likewise. * elf32-hppa.c: Likewise. * elf32-ppc.c: Likewise. * elf32-score.c: Likewise. * elf32-score7.c: Likewise. * elf64-ppc.c: Likewise. * elfxx-aarch64.c: Likewise. * elfxx-mips.c: Likewise. * cpu-ns32k.c: Add missing fall through comments. * elf-m10300.c: Likewise. * elf32-arm.c: Likewise. * elf32-avr.c: Likewise. * elf32-bfin.c: Likewise. * elf32-frv.c: Likewise. * elf32-i386.c: Likewise. * elf32-microblaze.c: Likewise. * elf32-nds32.c: Likewise. * elf32-ppc.c: Likewise. * elf32-rl78.c: Likewise. * elf32-rx.c: Likewise. * elf32-s390.c: Likewise. * elf32-sh.c: Likewise. * elf32-tic6x.c: Likewise. * elf64-ia64-vms.c: Likewise. * elf64-ppc.c: Likewise. * elf64-s390.c: Likewise. * elf64-x86-64.c: Likewise. * elflink.c: Likewise. * elfnn-aarch64.c: Likewise. * elfnn-ia64.c: Likewise. * ieee.c: Likewise. * oasys.c: Likewise. * pdp11.c: Likewise. * srec.c: Likewise. * versados.c: Likewise. opcodes/ * aarch64-opc.c: Spell fall through comments consistently. * i386-dis.c: Likewise. * aarch64-dis.c: Add missing fall through comments. * aarch64-opc.c: Likewise. * arc-dis.c: Likewise. * arm-dis.c: Likewise. * i386-dis.c: Likewise. * m68k-dis.c: Likewise. * mep-asm.c: Likewise. * ns32k-dis.c: Likewise. * sh-dis.c: Likewise. * tic4x-dis.c: Likewise. * tic6x-dis.c: Likewise. * vax-dis.c: Likewise. binutils/ * dlltool.c: Spell fall through comments consistently. * objcopy.c: Likewise. * readelf.c: Likewise. * dwarf.c: Add missing fall through comments. * elfcomm.c: Likewise. * sysinfo.y: Likewise. * readelf.c: Likewise. Also remove extraneous comments. gas/ * app.c: Add missing fall through comments. * dw2gencfi.c: Likewise. * expr.c: Likewise. * config/tc-alpha.c: Likewise. * config/tc-arc.c: Likewise. * config/tc-arm.c: Likewise. * config/tc-cr16.c: Likewise. * config/tc-crx.c: Likewise. * config/tc-dlx.c: Likewise. * config/tc-h8300.c: Likewise. * config/tc-hppa.c: Likewise. * config/tc-i370.c: Likewise. * config/tc-i386.c: Likewise. * config/tc-i960.c: Likewise. * config/tc-ia64.c: Likewise. * config/tc-m68hc11.c: Likewise. * config/tc-m68k.c: Likewise. * config/tc-mep.c: Likewise. * config/tc-metag.c: Likewise. * config/tc-microblaze.c: Likewise. * config/tc-mips.c: Likewise. * config/tc-ns32k.c: Likewise. * config/tc-rx.c: Likewise. * config/tc-score.c: Likewise. * config/tc-score7.c: Likewise. * config/tc-sh.c: Likewise. * config/tc-tic4x.c: Likewise. * config/tc-vax.c: Likewise. * config/tc-xstormy16.c: Likewise. * config/tc-z80.c: Likewise. * config/tc-z8k.c: Likewise. * config/obj-elf.c: Likewise. * config/tc-i386.c: Likewise. * depend.c: Spell fall through comments consistently. * config/tc-arm.c: Likewise. * config/tc-d10v.c: Likewise. * config/tc-i960.c: Likewise. * config/tc-ia64.c: Likewise. * config/tc-m68k.c: Likewise. * config/tc-mcore.c: Likewise. * config/tc-mep.c: Likewise. * config/tc-ns32k.c: Likewise. * config/tc-visium.c: Likewise. * config/tc-xstormy16.c: Likewise. * config/tc-z8k.c: Likewise. gprof/ * gprof.c: Add missing fall through comments. ld/ * lexsup.c: Spell fall through comments consistently and add missing fall through comments.
2016-09-21[AArch64] Add SVE condition codesRichard Sandiford1-9/+40
SVE defines new names for existing NZCV conditions, to reflect the result of instructions like PTEST. This patch adds support for these names. The patch also adds comments to the disassembly output to show the alternative names of a condition code. For example: cinv x0, x1, cc becomes: cinv x0, x1, cc // cc = lo, ul, last and: b.cc f0 <...> becomes: b.cc f0 <...> // b.lo, b.ul, b.last Doing this for the SVE names follows the practice recommended by the SVE specification and is definitely useful when reading SVE code. If the feeling is that it's too distracting elsewhere, we could add an option to turn it off. include/ * opcode/aarch64.h (aarch64_cond): Bump array size to 4. opcodes/ * aarch64-dis.c (remove_dot_suffix): New function, split out from... (print_mnemonic_name): ...here. (print_comment): New function. (print_aarch64_insn): Call it. * aarch64-opc.c (aarch64_conds): Add SVE names. (aarch64_print_operand): Print alternative condition names in a comment. gas/ * config/tc-aarch64.c (opcode_lookup): Search for the end of a condition name, rather than assuming that it will have exactly 2 characters. (parse_operands): Likewise. * testsuite/gas/aarch64/alias.d: Add new condition-code comments to the expected output. * testsuite/gas/aarch64/beq_1.d: Likewise. * testsuite/gas/aarch64/float-fp16.d: Likewise. * testsuite/gas/aarch64/int-insns.d: Likewise. * testsuite/gas/aarch64/no-aliases.d: Likewise. * testsuite/gas/aarch64/programmer-friendly.d: Likewise. * testsuite/gas/aarch64/reloc-insn.d: Likewise. * testsuite/gas/aarch64/b_c_1.d, testsuite/gas/aarch64/b_c_1.s: New test. ld/ * testsuite/ld-aarch64/emit-relocs-280.d: Match branch comments. * testsuite/ld-aarch64/weak-undefined.d: Likewise.
2016-09-21[AArch64][SVE 31/32] Add SVE instructionsRichard Sandiford1-1/+43
This patch adds the SVE instruction definitions and associated OP_* enum values. include/ * opcode/aarch64.h (AARCH64_FEATURE_SVE): New macro. (OP_MOV_P_P, OP_MOV_Z_P_Z, OP_MOV_Z_V, OP_MOV_Z_Z, OP_MOV_Z_Zi) (OP_MOVM_P_P_P, OP_MOVS_P_P, OP_MOVZS_P_P_P, OP_MOVZ_P_P_P) (OP_NOTS_P_P_P_Z, OP_NOT_P_P_P_Z): New aarch64_ops. opcodes/ * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB) (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ) (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD) (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU) (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB) (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR) (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS) (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB) (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD) (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD) (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD) (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD) (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD) (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD) (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS) (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD) (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD) (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD) (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD) (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD) (OP_SVE_XWU, OP_SVE_XXU): New macros. (aarch64_feature_sve): New variable. (SVE): New macro. (_SVE_INSN): Likewise. (aarch64_opcode_table): Add SVE instructions. * aarch64-opc.h (extract_fields): Declare. * aarch64-opc-2.c: Regenerate. * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops. * aarch64-asm-2.c: Regenerate. * aarch64-dis.c (extract_fields): Make global. (do_misc_decoding): Handle the new SVE aarch64_ops. * aarch64-dis-2.c: Regenerate. gas/ * doc/c-aarch64.texi: Document the "sve" feature. * config/tc-aarch64.c (REG_TYPE_R_Z_BHSDQ_VZP): New register type. (get_reg_expected_msg): Handle it. (parse_operands): When parsing operands of an SVE instruction, disallow immediates that match REG_TYPE_R_Z_BHSDQ_VZP. (aarch64_features): Add an entry for SVE.
2016-09-21[AArch64][SVE 30/32] Add SVE instruction classesRichard Sandiford1-0/+107
The main purpose of the SVE aarch64_insn_classes is to describe how an index into an aarch64_opnd_qualifier_seq_t is represented in the instruction encoding. Other instructions usually use flags for this information, but (a) we're running out of those and (b) the iclass would otherwise be unused for SVE. include/ * opcode/aarch64.h (sve_cpy, sve_index, sve_limm, sve_misc) (sve_movprfx, sve_pred_zm, sve_shift_pred, sve_shift_unpred) (sve_size_bhs, sve_size_bhsd, sve_size_hsd, sve_size_sd): New aarch64_insn_classes. opcodes/ * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16) (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New aarch64_field_kinds. * aarch64-opc.c (fields): Add corresponding entries. * aarch64-asm.c (aarch64_get_variant): New function. (aarch64_encode_variant_using_iclass): Likewise. (aarch64_opcode_encode): Call it. * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function. (aarch64_opcode_decode): Call it.
2016-09-21[AArch64][SVE 28/32] Add SVE FP immediate operandsRichard Sandiford1-0/+45
This patch adds support for the new SVE floating-point immediate operands. One operand uses the same 8-bit encoding as base AArch64, but in a different position. The others use a single bit to select between two values. One of the single-bit operands is a choice between 0 and 1, where 0 is not a valid 8-bit encoding. I think the cleanest way of handling these single-bit immediates is therefore to use the IEEE float encoding itself as the immediate value and select between the two possible values when encoding and decoding. As described in the covering note for the patch that added F_STRICT, we get better error messages by accepting unsuffixed vector registers and leaving the qualifier matching code to report an error. This means that we carry on parsing the other operands, and so can try to parse FP immediates for invalid instructions like: fcpy z0, #2.5 In this case there is no suffix to tell us whether the immediate should be treated as single or double precision. Again, we get better error messages by picking one (arbitrary) immediate size and reporting an error for the missing suffix later. include/ * opcode/aarch64.h (AARCH64_OPND_SVE_FPIMM8): New aarch64_opnd. (AARCH64_OPND_SVE_I1_HALF_ONE, AARCH64_OPND_SVE_I1_HALF_TWO) (AARCH64_OPND_SVE_I1_ZERO_ONE): Likewise. opcodes/ * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP immediate operands. * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind. * aarch64-opc.c (fields): Add corresponding entry. (operand_general_constraint_met_p): Handle the new SVE FP immediate operands. (aarch64_print_operand): Likewise. * aarch64-opc-2.c: Regenerate. * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two) (ins_sve_float_zero_one): New inserters. * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function. (aarch64_ins_sve_float_half_two): Likewise. (aarch64_ins_sve_float_zero_one): Likewise. * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two) (ext_sve_float_zero_one): New extractors. * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function. (aarch64_ext_sve_float_half_two): Likewise. (aarch64_ext_sve_float_zero_one): Likewise. * aarch64-dis-2.c: Regenerate. gas/ * config/tc-aarch64.c (double_precision_operand_p): New function. (parse_operands): Use it to calculate the dp_p input to parse_aarch64_imm_float. Handle the new SVE FP immediate operands.
2016-09-21[AArch64][SVE 27/32] Add SVE integer immediate operandsRichard Sandiford1-17/+127
This patch adds the new SVE integer immediate operands. There are three kinds: - simple signed and unsigned ranges, but with new widths and positions. - 13-bit logical immediates. These have the same form as in base AArch64, but at a different bit position. In the case of the "MOV Zn.<T>, #<limm>" alias of DUPM, the logical immediate <limm> is not allowed to be a valid DUP immediate, since DUP is preferred over DUPM for constants that both instructions can handle. - a new 9-bit arithmetic immediate, of the form "<imm8>{, LSL #8}". In some contexts the operand is signed and in others it's unsigned. As an extension, we allow shifted immediates to be written as a single integer, e.g. "#256" is equivalent to "#1, LSL #8". We also use the shiftless form as the preferred disassembly, except for the special case of "#0, LSL #8" (a redundant encoding of 0). include/ * opcode/aarch64.h (AARCH64_OPND_SIMM5): New aarch64_opnd. (AARCH64_OPND_SVE_AIMM, AARCH64_OPND_SVE_ASIMM) (AARCH64_OPND_SVE_INV_LIMM, AARCH64_OPND_SVE_LIMM) (AARCH64_OPND_SVE_LIMM_MOV, AARCH64_OPND_SVE_SHLIMM_PRED) (AARCH64_OPND_SVE_SHLIMM_UNPRED, AARCH64_OPND_SVE_SHRIMM_PRED) (AARCH64_OPND_SVE_SHRIMM_UNPRED, AARCH64_OPND_SVE_SIMM5) (AARCH64_OPND_SVE_SIMM5B, AARCH64_OPND_SVE_SIMM6) (AARCH64_OPND_SVE_SIMM8, AARCH64_OPND_SVE_UIMM3) (AARCH64_OPND_SVE_UIMM7, AARCH64_OPND_SVE_UIMM8) (AARCH64_OPND_SVE_UIMM8_53): Likewise. (aarch64_sve_dupm_mov_immediate_p): Declare. opcodes/ * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE integer immediate operands. * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5) (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9) (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds. * aarch64-opc.c (fields): Add corresponding entries. (operand_general_constraint_met_p): Handle the new SVE integer immediate operands. (aarch64_print_operand): Likewise. (aarch64_sve_dupm_mov_immediate_p): New function. * aarch64-opc-2.c: Regenerate. * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm) (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters. * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from... (aarch64_ins_limm): ...here. (aarch64_ins_inv_limm): New function. (aarch64_ins_sve_aimm): Likewise. (aarch64_ins_sve_asimm): Likewise. (aarch64_ins_sve_limm_mov): Likewise. (aarch64_ins_sve_shlimm): Likewise. (aarch64_ins_sve_shrimm): Likewise. * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm) (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors. * aarch64-dis.c (decode_limm): New function, split out from... (aarch64_ext_limm): ...here. (aarch64_ext_inv_limm): New function. (decode_sve_aimm): Likewise. (aarch64_ext_sve_aimm): Likewise. (aarch64_ext_sve_asimm): Likewise. (aarch64_ext_sve_limm_mov): Likewise. (aarch64_top_bit): Likewise. (aarch64_ext_sve_shlimm): Likewise. (aarch64_ext_sve_shrimm): Likewise. * aarch64-dis-2.c: Regenerate. gas/ * config/tc-aarch64.c (parse_operands): Handle the new SVE integer immediate operands.
2016-09-21[AArch64][SVE 26/32] Add SVE MUL VL addressing modesRichard Sandiford1-0/+72
This patch adds support for addresses of the form: [<base>, #<offset>, MUL VL] This involves adding a new AARCH64_MOD_MUL_VL modifier, which is why I split it out from the other addressing modes. For LD2, LD3 and LD4, the offset must be a multiple of the structure size, so for LD3 the possible values are 0, 3, 6, .... The patch therefore extends value_aligned_p to handle non-power-of-2 alignments. include/ * opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4xVL): New aarch64_opnd. (AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, AARCH64_OPND_SVE_ADDR_RI_S4x3xVL) (AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, AARCH64_OPND_SVE_ADDR_RI_S6xVL) (AARCH64_OPND_SVE_ADDR_RI_S9xVL): Likewise. (AARCH64_MOD_MUL_VL): New aarch64_modifier_kind. opcodes/ * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL operands. * aarch64-opc.c (aarch64_operand_modifiers): Initialize the AARCH64_MOD_MUL_VL entry. (value_aligned_p): Cope with non-power-of-two alignments. (operand_general_constraint_met_p): Handle the new MUL VL addresses. (print_immediate_offset_address): Likewise. (aarch64_print_operand): Likewise. * aarch64-opc-2.c: Regenerate. * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl) (ins_sve_addr_ri_s9xvl): New inserters. * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function. (aarch64_ins_sve_addr_ri_s6xvl): Likewise. (aarch64_ins_sve_addr_ri_s9xvl): Likewise. * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl) (ext_sve_addr_ri_s9xvl): New extractors. * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function. (aarch64_ext_sve_addr_ri_s4xvl): Likewise. (aarch64_ext_sve_addr_ri_s6xvl): Likewise. (aarch64_ext_sve_addr_ri_s9xvl): Likewise. * aarch64-dis-2.c: Regenerate. gas/ * config/tc-aarch64.c (SHIFTED_NONE, SHIFTED_MUL_VL): New parse_shift_modes. (parse_shift): Handle SHIFTED_MUL_VL. (parse_address_main): Add an imm_shift_mode parameter. (parse_address, parse_sve_address): Update accordingly. (parse_operands): Handle MUL VL addressing modes.
2016-09-21[AArch64][SVE 25/32] Add support for SVE addressing modesRichard Sandiford1-0/+146
This patch adds most of the new SVE addressing modes and associated operands. A follow-on patch adds MUL VL, since handling it separately makes the changes easier to read. The patch also introduces a new "operand-dependent data" field to the operand flags, based closely on the existing one for opcode flags. For SVE this new field needs only 2 bits, but it could be widened in future if necessary. include/ * opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_U6): New aarch64_opnd. (AARCH64_OPND_SVE_ADDR_RI_U6x2, AARCH64_OPND_SVE_ADDR_RI_U6x4) (AARCH64_OPND_SVE_ADDR_RI_U6x8, AARCH64_OPND_SVE_ADDR_RR) (AARCH64_OPND_SVE_ADDR_RR_LSL1, AARCH64_OPND_SVE_ADDR_RR_LSL2) (AARCH64_OPND_SVE_ADDR_RR_LSL3, AARCH64_OPND_SVE_ADDR_RX) (AARCH64_OPND_SVE_ADDR_RX_LSL1, AARCH64_OPND_SVE_ADDR_RX_LSL2) (AARCH64_OPND_SVE_ADDR_RX_LSL3, AARCH64_OPND_SVE_ADDR_RZ) (AARCH64_OPND_SVE_ADDR_RZ_LSL1, AARCH64_OPND_SVE_ADDR_RZ_LSL2) (AARCH64_OPND_SVE_ADDR_RZ_LSL3, AARCH64_OPND_SVE_ADDR_RZ_XTW_14) (AARCH64_OPND_SVE_ADDR_RZ_XTW_22, AARCH64_OPND_SVE_ADDR_RZ_XTW1_14) (AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, AARCH64_OPND_SVE_ADDR_RZ_XTW2_14) (AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, AARCH64_OPND_SVE_ADDR_RZ_XTW3_14) (AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, AARCH64_OPND_SVE_ADDR_ZI_U5) (AARCH64_OPND_SVE_ADDR_ZI_U5x2, AARCH64_OPND_SVE_ADDR_ZI_U5x4) (AARCH64_OPND_SVE_ADDR_ZI_U5x8, AARCH64_OPND_SVE_ADDR_ZZ_LSL) (AARCH64_OPND_SVE_ADDR_ZZ_SXTW, AARCH64_OPND_SVE_ADDR_ZZ_UXTW): Likewise. opcodes/ * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE address operands. * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14) (FLD_SVE_xs_22): New aarch64_field_kinds. (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags. (get_operand_specific_data): New function. * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14 and FLD_SVE_xs_22. (operand_general_constraint_met_p): Handle the new SVE address operands. (sve_reg): New array. (get_addr_sve_reg_name): New function. (aarch64_print_operand): Handle the new SVE address operands. * aarch64-opc-2.c: Regenerate. * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl) (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl) (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters. * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function. (aarch64_ins_sve_addr_rr_lsl): Likewise. (aarch64_ins_sve_addr_rz_xtw): Likewise. (aarch64_ins_sve_addr_zi_u5): Likewise. (aarch64_ins_sve_addr_zz): Likewise. (aarch64_ins_sve_addr_zz_lsl): Likewise. (aarch64_ins_sve_addr_zz_sxtw): Likewise. (aarch64_ins_sve_addr_zz_uxtw): Likewise. * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl) (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl) (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors. * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function. (aarch64_ext_sve_addr_ri_u6): Likewise. (aarch64_ext_sve_addr_rr_lsl): Likewise. (aarch64_ext_sve_addr_rz_xtw): Likewise. (aarch64_ext_sve_addr_zi_u5): Likewise. (aarch64_ext_sve_addr_zz): Likewise. (aarch64_ext_sve_addr_zz_lsl): Likewise. (aarch64_ext_sve_addr_zz_sxtw): Likewise. (aarch64_ext_sve_addr_zz_uxtw): Likewise. * aarch64-dis-2.c: Regenerate. gas/ * config/tc-aarch64.c (REG_TYPE_SVE_BASE, REG_TYPE_SVE_OFFSET): New register types. (get_reg_expected_msg): Handle them. (aarch64_addr_reg_parse): New function, split out from aarch64_reg_parse_32_64. Handle Z registers too. (aarch64_reg_parse_32_64): Call it. (parse_address_main): Add base_qualifier, offset_qualifier, base_type and offset_type parameters. Handle SVE base and offset registers. (parse_address): Update call to parse_address_main. (parse_sve_address): New function. (parse_operands): Parse the new SVE address operands.
2016-09-21[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALEDRichard Sandiford1-0/+20
Some SVE instructions count the number of elements in a given vector pattern and allow a scale factor of [1, 16] to be applied to the result. This scale factor is written ", MUL #n", where "MUL" is a new operator. E.g.: UQINCD X0, POW2, MUL #2 This patch adds support for this kind of operand. All existing operators were shifts of some kind, so there was a natural range of [0, 63] regardless of context. This was then narrowered further by later checks (e.g. to [0, 31] when used for 32-bit values). In contrast, MUL doesn't really have a natural context-independent range. Rather than pick one arbitrarily, it seemed better to make the "shift" amount a full 64-bit value and leave the range test to the usual operand-checking code. I've rearranged the fields of aarch64_opnd_info so that this doesn't increase the size of the structure (although I don't think its size is critical anyway). include/ * opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN_SCALED): New aarch64_opnd. (AARCH64_MOD_MUL): New aarch64_modifier_kind. (aarch64_opnd_info): Make shifter.amount an int64_t and rearrange the fields. opcodes/ * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for AARCH64_OPND_SVE_PATTERN_SCALED. * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind. * aarch64-opc.c (fields): Add a corresponding entry. (set_multiplier_out_of_range_error): New function. (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL. (operand_general_constraint_met_p): Handle AARCH64_OPND_SVE_PATTERN_SCALED. (print_register_offset_address): Use PRIi64 to print the shift amount. (aarch64_print_operand): Likewise. Handle AARCH64_OPND_SVE_PATTERN_SCALED. * aarch64-opc-2.c: Regenerate. * aarch64-asm.h (ins_sve_scale): New inserter. * aarch64-asm.c (aarch64_ins_sve_scale): New function. * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_sve_scale): New inserter. * aarch64-dis.c (aarch64_ext_sve_scale): New function. * aarch64-dis-2.c: Regenerate. gas/ * config/tc-aarch64.c (SHIFTED_MUL): New parse_shift_mode. (parse_shift): Handle it. Reject AARCH64_MOD_MUL for all other shift modes. Skip range tests for AARCH64_MOD_MUL. (process_omitted_operand): Handle AARCH64_OPND_SVE_PATTERN_SCALED. (parse_operands): Likewise.
2016-09-21[AArch64][SVE 21/32] Add Zn and Pn registersRichard Sandiford1-0/+34
This patch adds the Zn and Pn registers, and associated fields and operands. include/ * opcode/aarch64.h (AARCH64_OPND_CLASS_SVE_REG): New aarch64_operand_class. (AARCH64_OPND_CLASS_PRED_REG): Likewise. (AARCH64_OPND_SVE_Pd, AARCH64_OPND_SVE_Pg3, AARCH64_OPND_SVE_Pg4_5) (AARCH64_OPND_SVE_Pg4_10, AARCH64_OPND_SVE_Pg4_16) (AARCH64_OPND_SVE_Pm, AARCH64_OPND_SVE_Pn, AARCH64_OPND_SVE_Pt) (AARCH64_OPND_SVE_Za_5, AARCH64_OPND_SVE_Za_16, AARCH64_OPND_SVE_Zd) (AARCH64_OPND_SVE_Zm_5, AARCH64_OPND_SVE_Zm_16, AARCH64_OPND_SVE_Zn) (AARCH64_OPND_SVE_Zn_INDEX, AARCH64_OPND_SVE_ZnxN) (AARCH64_OPND_SVE_Zt, AARCH64_OPND_SVE_ZtxN): New aarch64_opnds. opcodes/ * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands. * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5) (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt) (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16) (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds. * aarch64-opc.c (fields): Add corresponding entries here. (operand_general_constraint_met_p): Check that SVE register lists have the correct length. Check the ranges of SVE index registers. Check for cases where p8-p15 are used in 3-bit predicate fields. (aarch64_print_operand): Handle the new SVE operands. * aarch64-opc-2.c: Regenerate. * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters. * aarch64-asm.c (aarch64_ins_sve_index): New function. (aarch64_ins_sve_reglist): Likewise. * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors. * aarch64-dis.c (aarch64_ext_sve_index): New function. (aarch64_ext_sve_reglist): Likewise. * aarch64-dis-2.c: Regenerate. gas/ * config/tc-aarch64.c (NTA_HASVARWIDTH): New macro. (AARCH64_REG_TYPES): Add ZN and PN. (get_reg_expected_msg): Handle them. (parse_vector_type_for_operand): Add a reg_type parameter. Skip the width for Zn and Pn registers. (parse_typed_reg): Extend vector handling to Zn and Pn. Update the call to parse_vector_type_for_operand. Set HASVARTYPE for Zn and Pn, expecting the width to be 0. (parse_vector_reg_list): Restrict error about [BHSD]nn operands to REG_TYPE_VN. (vectype_to_qualifier): Use S_[BHSD] qualifiers for NTA_HASVARWIDTH. (parse_operands): Handle the new Zn and Pn operands. (REGSET16): New macro, split out from... (REGSET31): ...here. (reg_names): Add Zn and Pn entries.
2016-09-21[AArch64][SVE 16/32] Use specific insert/extract methods for fpimmRichard Sandiford1-3/+11
FPIMM used the normal "imm" insert/extract methods, with a specific test for FPIMM in the extract method. SVE needs to use the same extractors, so rather than add extra checks for specific operand types, it seemed cleaner to use a separate insert/extract method. opcodes/ * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm for FPIMM. * aarch64-asm.h (ins_fpimm): New inserter. * aarch64-asm.c (aarch64_ins_fpimm): New function. * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_fpimm): New extractor. * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test. (aarch64_ext_fpimm): New function. * aarch64-dis-2.c: Regenerate.
2016-09-21[AArch64][SVE 15/32] Add {insert,extract}_all_fields helpersRichard Sandiford1-7/+21
Several of the SVE operands use the aarch64_operand fields array to store the fields that make up the operand, rather than hard-coding the names in the C code. This patch adds helpers for inserting and extracting those fields. opcodes/ * aarch64-asm.c: Include libiberty.h. (insert_fields): New function. (aarch64_ins_imm): Use it. * aarch64-dis.c (extract_fields): New function. (aarch64_ext_imm): Use it.
2016-04-28Add support to AArch64 disassembler for verifying instructions. Add ↵Nick Clifton1-0/+8
verifier for LDPSW. PR target/19722 opcodes * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present. * aarch64-opc.c (verify_ldpsw): New function. * aarch64-opc.h (verify_ldpsw): New prototype. * aarch64-tbl.h: Add initialiser for verifier field. (LDPSW): Set verifier to verify_ldpsw. binutils* testsuite/binutils-all/aarch64/illegal.s: New test. * testsuite/binutils-all/aarch64/illegal.d: New test driver. include * opcode/aarch64.h (struct aarch64_opcode): Add verifier field.
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