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path: root/opcodes/aarch64-dis.c
AgeCommit message (Expand)AuthorFilesLines
2020-02-26Indent labelsAlan Modra1-1/+1
2020-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2019-12-16ubsan: aarch64: left shift of negative valueAlan Modra1-9/+6
2019-12-11aarch64 disassembler infinite loopAlan Modra1-0/+2
2019-11-07[binutils][aarch64] Bfloat16 enablement [2/X]Matthew Malcomson1-0/+1
2019-07-01[gas][aarch64][SVE2] Fix pmull{t,b} requirement on SVE2-AESMatthew Malcomson1-8/+5
2019-05-09[binutils][aarch64] New sve_size_tsz_bhs iclass.Matthew Malcomson1-0/+11
2019-05-09[binutils][aarch64] New sve_shift_tsz_bhsd iclass.Matthew Malcomson1-0/+11
2019-05-09[binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand.Matthew Malcomson1-0/+11
2019-05-09[binutils][aarch64] New sve_size_013 iclass.Matthew Malcomson1-0/+10
2019-05-09[binutils][aarch64] New sve_size_bh iclass.Matthew Malcomson1-0/+1
2019-05-09[binutils][aarch64] New sve_size_sd2 iclass.Matthew Malcomson1-0/+4
2019-05-09[binutils][aarch64] New iclass sve_size_hsd2.Matthew Malcomson1-0/+7
2019-03-25AArch64: Have -D override mapping symbol as documented.Tamar Christina1-1/+2
2019-03-25AArch64: Fix AArch64 disassembler mapping symbol searchTamar Christina1-6/+38
2019-03-25AArch64: Fix disassembler bug with out-of-order sectionsTamar Christina1-1/+6
2019-01-25AArch64: Remove ldgv and stgv instructions from Armv8.5-A Memory Tagging Exte...Sudi Das1-17/+0
2019-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2018-11-12[BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging ExtensionSudakshina Das1-0/+17
2018-11-12[BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging Exten...Sudakshina Das1-1/+2
2018-11-12[BINUTILS, AARCH64, 2/8] Add Tag generation instructions in Memory Tagging Ex...Sudakshina Das1-0/+2
2018-10-09[PATCH, BINUTILS, AARCH64, 7/9] Add BTI instructionSudakshina Das1-1/+1
2018-10-09[PATCH, BINUTILS, AARCH64, 4/9] Add Execution and Data Restriction instructionsSudakshina Das1-0/+6
2018-10-03AArch64: Constraint disassembler and assembler changes.Tamar Christina1-7/+59
2018-10-03AArch64: Refactor verifiers to make more general.Tamar Christina1-1/+2
2018-10-03AArch64: Refactor err_type.Tamar Christina1-13/+8
2018-10-03AArch64: Wire through instr_sequenceTamar Christina1-0/+3
2018-06-29Fix AArch64 encodings for by element instructions.Tamar Christina1-5/+14
2018-05-15Implement Read/Write constraints on system registers on AArch64Tamar Christina1-1/+16
2018-05-15Allow non-fatal errors to be emitted and for disassembly notes be placed on A...Tamar Christina1-2/+25
2018-05-15Modify AArch64 Assembly and disassembly functions to be able to fail and repo...Tamar Christina1-233/+299
2018-05-01Fix unintialized memory in aarch64 opcodes.Tamar Christina1-3/+3
2018-03-03opcodes error messagesAlan Modra1-1/+1
2018-01-03Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2017-12-19Correct disassembly of dot product instructions.Tamar Christina1-1/+1
2017-12-11[Binutils][Objdump]Check symbol section information while search a mapping sy...Renlin Li1-3/+5
2017-11-09Adds the new Fields and Operand types for the new instructions in Armv8.4-a.Tamar Christina1-0/+27
2017-06-28[AArch64] Add dot product support for AArch64 to binutilsTamar Christina1-0/+15
2017-06-15Prevent address violation problem when disassembling corrupt aarch64 binary.Nick Clifton1-0/+3
2017-06-14Don't use print_insn_XXX in GDBYao Qi1-1/+1
2017-05-18Don't compare boolean values against TRUE or FALSEAlan Modra1-4/+4
2017-02-24[AArch64] Additional SVE instructionsRichard Sandiford1-31/+48
2017-01-02Update year range in copyright notice of all files.Alan Modra1-1/+1
2016-11-18[AArch64] Add ARMv8.3 FCMLA and FCADD instructionsSzabolcs Nagy1-0/+42
2016-11-18[AArch64] Add ARMv8.3 combined pointer authentication load instructionsSzabolcs Nagy1-0/+21
2016-10-18AArch64/opcodes: Correct an `index' global shadowing errorMaciej W. Rozycki1-4/+4
2016-10-06-Wimplicit-fallthrough warning fixesAlan Modra1-0/+5
2016-09-21[AArch64] Add SVE condition codesRichard Sandiford1-9/+40
2016-09-21[AArch64][SVE 31/32] Add SVE instructionsRichard Sandiford1-1/+43
2016-09-21[AArch64][SVE 30/32] Add SVE instruction classesRichard Sandiford1-0/+107