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2016-08-23[AArch64] Add SVE condition codesusers/ARM/sveRichard Sandiford1-9/+40
2016-08-23[AArch64][SVE 31/32] Add SVE instructionsRichard Sandiford1-1/+43
2016-08-23[AArch64][SVE 30/32] Add SVE instruction classesRichard Sandiford1-0/+107
2016-08-23[AArch64][SVE 28/32] Add SVE FP immediate operandsRichard Sandiford1-0/+45
2016-08-23[AArch64][SVE 27/32] Add SVE integer immediate operandsRichard Sandiford1-17/+127
2016-08-23[AArch64][SVE 26/32] Add SVE MUL VL addressing modesRichard Sandiford1-0/+72
2016-08-23[AArch64][SVE 25/32] Add support for SVE addressing modesRichard Sandiford1-0/+146
2016-08-23[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALEDRichard Sandiford1-0/+20
2016-08-23[AArch64][SVE 21/32] Add Zn and Pn registersRichard Sandiford1-0/+34
2016-08-23[AArch64][SVE 16/32] Use specific insert/extract methods for fpimmRichard Sandiford1-3/+11
2016-08-23[AArch64][SVE 15/32] Add {insert,extract}_all_fields helpersRichard Sandiford1-7/+21
2016-04-28Add support to AArch64 disassembler for verifying instructions. Add verifier...Nick Clifton1-0/+8
2016-03-24More -Wstack-usage warnings: opcodes/aarch64-*Jan Kratochvil1-3/+2
2016-01-01Copyright update for binutilsAlan Modra1-1/+1
2015-12-14[AArch64][PATCH 11/14] Add support for the 2H vector type.Matthew Wahab1-1/+8
2015-12-11[AArch64][Patch 4/5] Support HINT aliases taking operands.Matthew Wahab1-0/+27
2015-12-10[AArch64][PATCH 1/2] Add support for ARMv8.2 DC CVAP instruction.Matthew Wahab1-2/+2
2015-11-27[AArch64] Add ARMv8.2 instructions BFC and REV64.Matthew Wahab1-0/+41
2015-11-27[AArch64] Let aliased instructions be their preferred form.Matthew Wahab1-1/+1
2015-10-28Pass noaliases_p to aarch64_decode_insnYao Qi1-5/+7
2015-10-07Avoid using 'template' C++ keywordYao Qi1-2/+2
2015-10-02[aarch64] expose disas_aarch64_insn and rename it to aarch64_decode_insnYao Qi1-4/+5
2015-10-02[aarch64] Remove argument pc from disas_aarch64_insnYao Qi1-3/+2
2015-01-02ChangeLog rotatation and copyright year updateAlan Modra1-1/+1
2014-09-03[PATCH/AArch64] Implement LSE featureJiong Wang1-0/+18
2014-03-26[AArch64 disassembler] Add missing checks of undefine encodings onYufeng Zhang1-3/+9
2014-03-05Update copyright yearsAlan Modra1-1/+1
2013-11-05gas/Yufeng Zhang1-4/+8
2013-08-23 PR binutils/15834Nick Clifton1-2/+2
2013-06-20bfd/Yufeng Zhang1-5/+0
2013-01-30include/opcode/Yufeng Zhang1-1/+20
2013-01-17include/opcode/Yufeng Zhang1-0/+1
2012-08-13Add support for 64-bit ARM architecture: AArch64Nick Clifton1-0/+2392
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