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path: root/opcodes/aarch64-dis-2.c
AgeCommit message (Expand)AuthorFilesLines
2021-01-11aarch64: Remove support for CSREKyrylo Tkachov1-1290/+1289
2021-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2020-11-09aarch64: Limit Rt register number for LS64 load/store instructionsPrzemyslaw Wirkus1-84/+85
2020-11-03[PATCH][GAS] aarch64: Add atomic 64-byte load/store instructions for Armv8.7Przemyslaw Wirkus1-1820/+1864
2020-10-30[PATCH][GAS] aarch64: Add WFIT instruction for Armv8.7-aPrzemyslaw Wirkus1-1250/+1252
2020-10-28aarch64: Add CSR PDEC instructionPrzemyslaw Wirkus1-1287/+1288
2020-10-28aarch64: Add WFET instruction for Armv8.7-aPrzemyslaw Wirkus1-1250/+1252
2020-10-28aarch64: Add DSB instruction Armv8.7-a variantPrzemyslaw Wirkus1-1305/+1309
2020-09-08aarch64: Add support for Armv8-R DFB aliasAlex Coplan1-1261/+1262
2020-04-30AArch64: add GAS support for UDF instructionAlex Coplan1-1900/+1912
2020-04-20[AArch64, Binutils] Add missing TSB instructionSudakshina Das1-1263/+1265
2020-04-20[AArch64, Binutils] Make hint space instructions valid for Armv8-aSudakshina Das1-1223/+1223
2020-01-27AArch64: Fix cfinv disassembly issuesTamar Christina1-1182/+1182
2020-01-03Arm64: correct uzp{1,2} mnemonicsJan Beulich1-2/+2
2020-01-03Arm64: correct 64-bit element fmmla encodingJan Beulich1-45/+45
2020-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2019-11-07[gas][aarch64] Add the v8.6 Data Gathering Hint mnemonic [10/X]Matthew Malcomson1-49/+50
2019-11-07[binutils][aarch64] Matrix Multiply extension enablement [8/X]Matthew Malcomson1-424/+733
2019-11-07[binutils][aarch64] Bfloat16 enablement [2/X]Matthew Malcomson1-68/+268
2019-07-01[gas][aarch64][SVE2] Fix pmull{t,b} requirement on SVE2-AESMatthew Malcomson1-286/+308
2019-05-09[binutils][aarch64] Add SVE2 instructions.Matthew Malcomson1-941/+4120
2019-05-09[binutils][aarch64] New SVE_SHLIMM_UNPRED_22 operand.Matthew Malcomson1-11/+12
2019-05-09[binutils][aarch64] New SVE_Zm4_11_INDEX operand.Matthew Malcomson1-7/+8
2019-05-09[binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand.Matthew Malcomson1-10/+11
2019-05-09[binutils][aarch64] New SVE_ADDR_ZX operand.Matthew Malcomson1-33/+34
2019-05-09[binutils][aarch64] New SVE_Zm3_11_INDEX operand.Matthew Malcomson1-7/+8
2019-05-09[binutils][aarch64] Introduce SVE_IMM_ROT3 operand.Matthew Malcomson1-19/+20
2019-05-01[BINUTILS, AArch64] Enable Transactional Memory ExtensionSudakshina Das1-940/+955
2019-04-11[BINUTILS, AArch64, 2/2] Update Store Allocation Tag instructionsSudakshina Das1-80/+81
2019-04-11[BINUTILS, AArch64, 1/2] Add new LDGM/STGM instructionSudakshina Das1-1231/+1253
2019-01-25AArch64: Add new STZGM instruction for Armv8.5-A Memory Tagging Extension.Sudi Das1-1248/+1259
2019-01-25AArch64: Remove ldgv and stgv instructions from Armv8.5-A Memory Tagging Exte...Sudi Das1-1305/+1281
2019-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2018-11-12[BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging ExtensionSudakshina Das1-1281/+1305
2018-11-12[BINUTILS, AARCH64, 5/8] Add Tag getting instruction in Memory Tagging ExtensionSudakshina Das1-1275/+1286
2018-11-12[BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging Exten...Sudakshina Das1-1416/+1528
2018-11-12[BINUTILS, AARCH64, 3/8] Add Pointer Arithmetic instructions in Memory Taggin...Sudakshina Das1-1514/+1538
2018-11-12[BINUTILS, AARCH64, 2/8] Add Tag generation instructions in Memory Tagging Ex...Sudakshina Das1-2323/+2351
2018-10-09[PATCH, BINUTILS, AARCH64, 7/9] Add BTI instructionSudakshina Das1-973/+975
2018-10-09[PATCH, BINUTILS, AARCH64, 4/9] Add Execution and Data Restriction instructionsSudakshina Das1-946/+950
2018-10-09[PATCH, BINUTILS, AARCH64, 3/9] Add instruction SB for ARMv8.5-ASudakshina Das1-913/+914
2018-10-09[PATCH, BINUTILS, AARCH64, 2/9] Add Data procoessing instructions for ARMv8.5-ASudakshina Das1-2125/+2215
2018-07-12This patch adds support for the SSBB and PSSBB speculation barrier instructio...Nick Clifton1-903/+906
2018-06-29Fix AArch64 encodings for by element instructions.Tamar Christina1-69/+70
2018-06-22Correct negs aliasing on AArch64.Tamar Christina1-3/+3
2018-05-16Fix disassembly mask for vector sdot on AArch64.Tamar Christina1-158/+178
2018-05-15Modify AArch64 Assembly and disassembly functions to be able to fail and repo...Tamar Christina1-62/+63
2018-03-28Enhance the AARCH64 assembler to support LDFF1xx instructions which use REG+R...Nick Clifton1-515/+548
2018-01-09Add support for the AArch64's CSDB instruction.James Greenhalgh1-899/+900
2018-01-03Update year range in copyright notice of binutils filesAlan Modra1-1/+1
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