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path: root/opcodes/aarch64-dis-2.c
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2016-09-21[AArch64][SVE 31/32] Add SVE instructionsRichard Sandiford1-115/+7931
2016-09-21[AArch64][SVE 29/32] Add new SVE core & FP register operandsRichard Sandiford1-10/+16
2016-09-21[AArch64][SVE 28/32] Add SVE FP immediate operandsRichard Sandiford1-25/+32
2016-09-21[AArch64][SVE 27/32] Add SVE integer immediate operandsRichard Sandiford1-38/+62
2016-09-21[AArch64][SVE 26/32] Add SVE MUL VL addressing modesRichard Sandiford1-18/+27
2016-09-21[AArch64][SVE 25/32] Add support for SVE addressing modesRichard Sandiford1-19/+57
2016-09-21[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALEDRichard Sandiford1-6/+8
2016-09-21[AArch64][SVE 23/32] Add SVE pattern and prfop operandsRichard Sandiford1-5/+7
2016-09-21[AArch64][SVE 21/32] Add Zn and Pn registersRichard Sandiford1-0/+20
2016-09-21[AArch64][SVE 16/32] Use specific insert/extract methods for fpimmRichard Sandiford1-1/+2
2016-01-01Copyright update for binutilsAlan Modra1-1/+1
2015-12-14[AArch64][PATCH 14/14] Support FP16 Adv.SIMD Scalar Shift By Immediate instru...Matthew Wahab1-674/+682
2015-12-14[AArch64][PATCH 13/14] Support FP16 Adv.SIMD Shift By Immediate instructions.Matthew Wahab1-898/+903
2015-12-14[AArch64][PATCH 12/14] Support FP16 Adv.SIMD Scalar Pairwise instructions.Matthew Wahab1-754/+809
2015-12-14[AArch64][PATCH 9/14] Support FP16 Adv.SIMD Modified Immediate instructions.Matthew Wahab1-1154/+1156
2015-12-14[AArch64][PATCH 8/14] Support FP16 Adv.SIMD Across Lanes instructions.Matthew Wahab1-1264/+1308
2015-12-14[AArch64][PATCH 7/14] Support FP16 Scalar Indexed Element instructions.Matthew Wahab1-863/+907
2015-12-14[AArch64][PATCH 6/14] Support FP16 Vector Indexed Element instructions.Matthew Wahab1-1184/+1228
2015-12-14[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.Matthew Wahab1-874/+1094
2015-12-14[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.Matthew Wahab1-1385/+1704
2015-12-14[AArch64][PATCH 3/14] Support ARMv8.2 FP16 Scalar Three Same instructions.Matthew Wahab1-727/+826
2015-12-14[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.Matthew Wahab1-978/+1242
2015-12-11[AArch64][Patch 5/5] Add instruction PSB CSYNCMatthew Wahab1-18/+21
2015-12-10[AArch64][PATCH 1/2] Add support for RAS instruction ESB.Matthew Wahab1-18/+19
2015-11-27[AArch64][PATCH 3/3] Add floating-point FP16 instructionsMatthew Wahab1-437/+537
2015-11-27[AArch64] Add ARMv8.2 instruction alias REV64.Matthew Wahab1-494/+496
2015-11-27[AArch64] Add ARMv8.2 instructions BFC and REV64.Matthew Wahab1-548/+549
2015-11-27[AArch64] Let aliased instructions be their preferred form.Matthew Wahab1-0/+95
2015-06-02[AArch64] Support for ARMv8.1a Adv.SIMD instructionsMatthew Wahab1-1005/+1093
2015-06-02[AArch64] Support for ARMv8.1a Limited Ordering Regions extensionMatthew Wahab1-264/+321
2015-03-10[AARCH64] Remove Load/Store register (unscaled immediate) alias.Jiong Wang1-286/+274
2015-01-02ChangeLog rotatation and copyright year updateAlan Modra1-1/+1
2014-09-03[PATCH/AArch64] Generic support for all system registers using mrs and msrJiong Wang1-99/+21
2014-09-03[PATCH/AArch64] Implement LSE featureJiong Wang1-164/+1578
2014-03-05Update copyright yearsAlan Modra1-1/+1
2013-11-05gas/Yufeng Zhang1-12/+13
2013-02-28include/opcode/Yufeng Zhang1-290/+378
2013-01-30include/opcode/Yufeng Zhang1-501/+505
2012-08-13Add support for 64-bit ARM architecture: AArch64Nick Clifton1-0/+7655
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