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2016-10-11[AArch64] PR target/20666, fix wrong encoding of new introduced BFC pseudoJiong Wang1-1/+1
2016-09-21[AArch64][SVE 31/32] Add SVE instructionsRichard Sandiford1-0/+43
2016-09-21[AArch64][SVE 30/32] Add SVE instruction classesRichard Sandiford1-0/+84
2016-09-21[AArch64][SVE 28/32] Add SVE FP immediate operandsRichard Sandiford1-0/+45
2016-09-21[AArch64][SVE 27/32] Add SVE integer immediate operandsRichard Sandiford1-6/+91
2016-09-21[AArch64][SVE 26/32] Add SVE MUL VL addressing modesRichard Sandiford1-0/+50
2016-09-21[AArch64][SVE 25/32] Add support for SVE addressing modesRichard Sandiford1-0/+108
2016-09-21[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALEDRichard Sandiford1-0/+13
2016-09-21[AArch64][SVE 21/32] Add Zn and Pn registersRichard Sandiford1-0/+27
2016-09-21[AArch64][SVE 16/32] Use specific insert/extract methods for fpimmRichard Sandiford1-0/+10
2016-09-21[AArch64][SVE 15/32] Add {insert,extract}_all_fields helpersRichard Sandiford1-7/+21
2016-09-21[AArch64][SVE 14/32] Make aarch64_logical_immediate_p take an element sizeRichard Sandiford1-2/+2
2016-01-01Copyright update for binutilsAlan Modra1-1/+1
2015-12-11[AArch64][Patch 4/5] Support HINT aliases taking operands.Matthew Wahab1-0/+13
2015-11-27[AArch64] Add ARMv8.2 instructions BFC and REV64.Matthew Wahab1-0/+34
2015-01-02ChangeLog rotatation and copyright year updateAlan Modra1-1/+1
2014-09-03[PATCH/AArch64] Implement LSE featureJiong Wang1-0/+8
2014-03-05Update copyright yearsAlan Modra1-1/+1
2013-08-23 PR binutils/15834Nick Clifton1-2/+2
2013-05-13gas/Yufeng Zhang1-1/+0
2013-01-30include/opcode/Yufeng Zhang1-1/+17
2013-01-17include/opcode/Yufeng Zhang1-1/+5
2012-10-18 * aarch64-asm.c (aarch64_ins_ldst_reglist): InitializeKai Tietz1-5/+5
2012-09-172012-09-17 Yufeng Zhang <yufeng.zhang@arm.com>Richard Earnshaw1-5/+6
2012-08-13Add support for 64-bit ARM architecture: AArch64Nick Clifton1-0/+1268