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path: root/opcodes/aarch64-asm-2.c
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2016-11-18[AArch64] Add ARMv8.3 javascript floating-point conversion instructionSzabolcs Nagy1-306/+306
2016-11-18[AArch64] Add ARMv8.3 combined pointer authentication load instructionsSzabolcs Nagy1-324/+326
2016-11-11[AArch64] Add ARMv8.3 combined pointer authentication branch instructionsSzabolcs Nagy1-406/+406
2016-11-11[AArch64] Add ARMv8.3 PACGA instructionSzabolcs Nagy1-399/+400
2016-11-11[AArch64] Add ARMv8.3 single source PAC instructionsSzabolcs Nagy1-389/+389
2016-11-11[AArch64] Add ARMv8.3 instructions which are in the NOP spaceSzabolcs Nagy1-127/+140
2016-09-21[AArch64][SVE 31/32] Add SVE instructionsRichard Sandiford1-0/+119
2016-09-21[AArch64][SVE 29/32] Add new SVE core & FP register operandsRichard Sandiford1-10/+16
2016-09-21[AArch64][SVE 28/32] Add SVE FP immediate operandsRichard Sandiford1-25/+32
2016-09-21[AArch64][SVE 27/32] Add SVE integer immediate operandsRichard Sandiford1-38/+62
2016-09-21[AArch64][SVE 26/32] Add SVE MUL VL addressing modesRichard Sandiford1-18/+27
2016-09-21[AArch64][SVE 25/32] Add support for SVE addressing modesRichard Sandiford1-19/+57
2016-09-21[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALEDRichard Sandiford1-6/+8
2016-09-21[AArch64][SVE 23/32] Add SVE pattern and prfop operandsRichard Sandiford1-5/+7
2016-09-21[AArch64][SVE 21/32] Add Zn and Pn registersRichard Sandiford1-0/+20
2016-09-21[AArch64][SVE 16/32] Use specific insert/extract methods for fpimmRichard Sandiford1-1/+2
2016-01-01Copyright update for binutilsAlan Modra1-1/+1
2015-12-14[AArch64][PATCH 14/14] Support FP16 Adv.SIMD Scalar Shift By Immediate instru...Matthew Wahab1-304/+304
2015-12-14[AArch64][PATCH 13/14] Support FP16 Adv.SIMD Shift By Immediate instructions.Matthew Wahab1-316/+316
2015-12-14[AArch64][PATCH 12/14] Support FP16 Adv.SIMD Scalar Pairwise instructions.Matthew Wahab1-304/+304
2015-12-14[AArch64][PATCH 9/14] Support FP16 Adv.SIMD Modified Immediate instructions.Matthew Wahab1-344/+344
2015-12-14[AArch64][PATCH 8/14] Support FP16 Adv.SIMD Across Lanes instructions.Matthew Wahab1-343/+343
2015-12-14[AArch64][PATCH 7/14] Support FP16 Scalar Indexed Element instructions.Matthew Wahab1-308/+308
2015-12-14[AArch64][PATCH 6/14] Support FP16 Vector Indexed Element instructions.Matthew Wahab1-343/+343
2015-12-14[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.Matthew Wahab1-308/+308
2015-12-14[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.Matthew Wahab1-332/+332
2015-12-14[AArch64][PATCH 3/14] Support ARMv8.2 FP16 Scalar Three Same instructions.Matthew Wahab1-304/+304
2015-12-14[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.Matthew Wahab1-328/+328
2015-12-11[AArch64][Patch 5/5] Add instruction PSB CSYNCMatthew Wahab1-6/+9
2015-12-10[AArch64][PATCH 1/2] Add support for RAS instruction ESB.Matthew Wahab1-6/+7
2015-11-27[AArch64][PATCH 3/3] Add floating-point FP16 instructionsMatthew Wahab1-211/+211
2015-11-27[AArch64] Add ARMv8.2 instruction alias REV64.Matthew Wahab1-255/+259
2015-11-27[AArch64] Add ARMv8.2 instructions BFC and REV64.Matthew Wahab1-285/+286
2015-11-27[AArch64] Let aliased instructions be their preferred form.Matthew Wahab1-0/+95
2015-06-02[AArch64] Support for ARMv8.1a Adv.SIMD instructionsMatthew Wahab1-190/+190
2015-06-02[AArch64] Support for ARMv8.1a Limited Ordering Regions extensionMatthew Wahab1-125/+125
2015-03-10[AARCH64] Remove Load/Store register (unscaled immediate) alias.Jiong Wang1-161/+125
2015-01-02ChangeLog rotatation and copyright year updateAlan Modra1-1/+1
2014-09-03[PATCH/AArch64] Implement LSE featureJiong Wang1-51/+195
2014-03-05Update copyright yearsAlan Modra1-1/+1
2013-11-05gas/Yufeng Zhang1-12/+13
2013-02-28include/opcode/Yufeng Zhang1-67/+67
2013-01-30include/opcode/Yufeng Zhang1-103/+115
2012-08-13Add support for 64-bit ARM architecture: AArch64Nick Clifton1-0/+345
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