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path: root/opcodes/aarch64-asm-2.c
AgeCommit message (Expand)AuthorFilesLines
2023-03-30aarch64: Add the RPRFM instructionRichard Sandiford1-68/+69
2023-03-30aarch64: Add new SVE dot-product instructionsRichard Sandiford1-34/+35
2023-03-30aarch64: Add the SME2 shift instructionsRichard Sandiford1-10/+13
2023-03-30aarch64: Add the SME2 MLALL and MLSLL instructionsRichard Sandiford1-15/+20
2023-03-30aarch64: Add the SME2 MLAL and MLSL instructionsRichard Sandiford1-16/+20
2023-03-30aarch64: Add the SME2 FMLA and FMLS instructionsRichard Sandiford1-8/+10
2023-03-30aarch64: Add the SME2 ADD and SUB instructionsRichard Sandiford1-25/+26
2023-03-30aarch64: Add the SME2 ZT0 instructionsRichard Sandiford1-8/+17
2023-03-30aarch64: Add the SME2 predicate-related instructionsRichard Sandiford1-20/+31
2023-03-30aarch64: Add the SME2 multivector LD1 and ST1 instructionsRichard Sandiford1-20/+24
2023-03-30aarch64: Add the SME2 MOVA instructionsRichard Sandiford1-12/+22
2023-03-30aarch64: Add support for predicate-as-counter registersRichard Sandiford1-117/+122
2023-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2022-11-14aarch64: Add support for Common Short Sequence Compression extensionAndre Vieira1-0/+2
2022-10-05Arm64: support CLEARBHB aliasJan Beulich1-105/+106
2022-01-02Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2021-12-02aarch64: Add support for +mopsRichard Sandiford1-0/+4
2021-11-17aarch64: [SME] SVE2 instructions added to support SMEPrzemyslaw Wirkus1-2/+4
2021-11-17aarch64: [SME] Add SME mode selection and state access instructionsPrzemyslaw Wirkus1-149/+151
2021-11-17aarch64: [SME] Add LD1x, ST1x, LDR and STR instructionsPrzemyslaw Wirkus1-36/+42
2021-11-17aarch64: [SME] Add ZERO instructionPrzemyslaw Wirkus1-1/+2
2021-11-17aarch64: [SME] Add MOV and MOVA instructionsPrzemyslaw Wirkus1-3/+6
2021-11-17aarch64: [SME] Add SME instructionsPrzemyslaw Wirkus1-2/+5
2021-03-31Use bool in opcodesAlan Modra1-1/+1
2021-01-11aarch64: Remove support for CSREKyrylo Tkachov1-124/+124
2021-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2020-11-09aarch64: Limit Rt register number for LS64 load/store instructionsPrzemyslaw Wirkus1-80/+81
2020-11-03[PATCH][GAS] aarch64: Add atomic 64-byte load/store instructions for Armv8.7Przemyslaw Wirkus1-343/+343
2020-10-30[PATCH][GAS] aarch64: Add WFIT instruction for Armv8.7-aPrzemyslaw Wirkus1-89/+92
2020-10-28aarch64: Add CSR PDEC instructionPrzemyslaw Wirkus1-122/+122
2020-10-28aarch64: Add WFET instruction for Armv8.7-aPrzemyslaw Wirkus1-89/+92
2020-10-28aarch64: Add DSB instruction Armv8.7-a variantPrzemyslaw Wirkus1-141/+146
2020-09-08aarch64: Add support for Armv8-R DFB aliasAlex Coplan1-98/+99
2020-04-30AArch64: add GAS support for UDF instructionAlex Coplan1-384/+385
2020-04-20[AArch64, Binutils] Add missing TSB instructionSudakshina Das1-102/+104
2020-04-20[AArch64, Binutils] Make hint space instructions valid for Armv8-aSudakshina Das1-109/+109
2020-01-27AArch64: Fix cfinv disassembly issuesTamar Christina1-87/+87
2020-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2019-11-07[binutils][aarch64] Matrix Multiply extension enablement [8/X]Matthew Malcomson1-38/+39
2019-05-09[binutils][aarch64] New SVE_SHLIMM_UNPRED_22 operand.Matthew Malcomson1-11/+12
2019-05-09[binutils][aarch64] New SVE_Zm4_11_INDEX operand.Matthew Malcomson1-7/+8
2019-05-09[binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand.Matthew Malcomson1-10/+11
2019-05-09[binutils][aarch64] New SVE_ADDR_ZX operand.Matthew Malcomson1-33/+34
2019-05-09[binutils][aarch64] New SVE_Zm3_11_INDEX operand.Matthew Malcomson1-7/+8
2019-05-09[binutils][aarch64] Introduce SVE_IMM_ROT3 operand.Matthew Malcomson1-19/+20
2019-05-01[BINUTILS, AArch64] Enable Transactional Memory ExtensionSudakshina Das1-137/+138
2019-04-11[BINUTILS, AArch64, 2/2] Update Store Allocation Tag instructionsSudakshina Das1-76/+77
2019-04-11[BINUTILS, AArch64, 1/2] Add new LDGM/STGM instructionSudakshina Das1-295/+295
2019-01-25AArch64: Add new STZGM instruction for Armv8.5-A Memory Tagging Extension.Sudi Das1-316/+316
2019-01-25AArch64: Remove ldgv and stgv instructions from Armv8.5-A Memory Tagging Exte...Sudi Das1-348/+346
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