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AgeCommit message (Expand)AuthorFilesLines
2018-07-23power9 mfupmc/mtupmcAlan Modra1-0/+6
2018-07-20MIPS/GAS: Split Loongson MMI Instructions from loongson2f/3aChenghua Xu1-0/+11
2018-07-19x86: fold narrowing VCVT* templatesJan Beulich1-0/+7
2018-07-19x86: fold VFPCLASSP{D,S} templatesJan Beulich1-0/+8
2018-07-19x86: fold various AVX512* templatesJan Beulich1-0/+9
2018-07-19x86: fold various AVX512DQ templatesJan Beulich1-0/+8
2018-07-19x86: fold various AVX512BW templatesJan Beulich1-0/+8
2018-07-19x86: fold various AVX512CD templatesJan Beulich1-0/+8
2018-07-19x86: fold various AVX512VL templates into their AVX512F counterpartsJan Beulich1-0/+10
2018-07-19x86: pre-process opcodes table before parsingJan Beulich1-0/+12
2018-07-18x86: Split vcvtps2{,u}qq and vcvttps2{,u}qqH.J. Lu1-0/+16
2018-07-12This patch adds support for the SSBB and PSSBB speculation barrier instructio...Nick Clifton1-0/+8
2018-07-12Add remainder of Em16 restrictions for AArch64 gas.Tamar Christina1-0/+8
2018-07-11Adds the speculation barrier instructions to the ARM assembler and disassembler.Sudakshina Das1-0/+6
2018-07-11x86: adjust monitor/mwait templatesJan Beulich1-0/+9
2018-07-11x86: drop {,reg16_}inoutportreg variablesJan Beulich1-0/+7
2018-07-11x86/Intel: accept memory operand size specifiers for CET insnsJan Beulich1-0/+6
2018-07-11x86: replace off-by-one OTMaxJan Beulich1-0/+6
2018-07-09S12Z/opcodes: Correct a `reg' global shadowing error for pre-4.8 GCCMaciej W. Rozycki1-0/+8
2018-07-06Fix SBO bit in disassembly mask for ldrah on AArch64.Tamar Christina1-0/+5
2018-07-06Fix the read/write flag for these registers on AArch64Tamar Christina1-0/+6
2018-07-02GDB PR tdep/8282: MIPS: Wire in `set disassembler-options'Maciej W. Rozycki1-0/+13
2018-07-02[ARM] Update bfd's Tag_CPU_arch knowledgeThomas Preud'homme1-0/+8
2018-06-29Fix AArch64 encodings for by element instructions.Tamar Christina1-0/+14
2018-06-26Updated translations.Nick Clifton1-0/+6
2018-06-26Fix spelling mistakes.Nick Clifton1-0/+4
2018-06-24Regenerate configure and pot files with updated binutils version number.Nick Clifton1-0/+5
2018-06-24Add 2.30 branch notes to ChangeLogs and NEWS files.Nick Clifton1-0/+4
2018-06-22Correct negs aliasing on AArch64.Tamar Christina1-0/+6
2018-06-21MIPS/opcodes: Fix a typo in `-M ginv' option descriptionMaciej W. Rozycki1-0/+5
2018-06-20RISC-V: Accept constant operands in la and llaSebastian Huber1-0/+6
2018-06-19Bump to autoconf 2.69 and automake 1.15.1Simon Marchi1-0/+8
2018-06-14MIPS: Add Global INValidate ASE supportFaraz Shahbazker1-0/+10
2018-06-13MIPS: Add CRC ASE supportScott Egerton1-0/+9
2018-06-08Prevent undefined FMOV instructions being accepted by the AArch64 assembler.Egeyar Bagcioglu1-0/+6
2018-06-06Fix xtensa "clobbered by longjmp" warningsAlan Modra1-0/+5
2018-06-04xtensa: use property tables for correct disassemblyMax Filippov1-0/+12
2018-06-01Bump version number to 2.30.52H.J. Lu1-0/+4
2018-06-01x86: fold MOV to/from segment register templatesJan Beulich1-0/+5
2018-06-01x86: don't emit REX.W for SLDT and STRJan Beulich1-0/+5
2018-06-01x86/Intel: accept "oword ptr" for INVPCIDJan Beulich1-0/+5
2018-06-01Make _bfd_error_handler available outside libbfdAlan Modra1-0/+8
2018-05-30Add znver2 support.Amit Pawar1-0/+5
2018-05-25s12z regenAlan Modra1-0/+5
2018-05-21Remove fake operand handling for extended mnemonics.Peter Bergner1-0/+14
2018-05-18Add support for the Freescale s12z processor.John Darrington1-0/+11
2018-05-18opcodes sources should not include libbfd.hAlan Modra1-0/+6
2018-05-17Updated simplified Chinese translation for the opcodes directory.Nick Clifton1-0/+4
2018-05-16Fix disassembly mask for vector sdot on AArch64.Tamar Christina1-0/+6
2018-05-15Implement Read/Write constraints on system registers on AArch64Tamar Christina1-0/+28
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