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AgeCommit message (Expand)AuthorFilesLines
2021-04-08PR27684, PowerPC missing mfsprg0 and othersAlan Modra1-0/+5
2021-04-08PR27676, PowerPC missing extended dcbt, dcbtst mnemonicsAlan Modra1-0/+8
2021-04-06Return symbol from symbol_at_address_funcAlan Modra1-0/+6
2021-04-05C99 opcodes configuryAlan Modra1-0/+12
2021-04-01Remove strneq macro and use startswith.Martin Liska1-0/+8
2021-04-01PR27675, PowerPC missing extended mnemonic mfummcr2Alan Modra1-0/+5
2021-03-31Use bool in opcodesAlan Modra1-0/+18
2021-03-31Remove bfd_stdint.hAlan Modra1-0/+14
2021-03-30x86: drop seg_entryJan Beulich1-0/+7
2021-03-30x86: drop REGNAM_{AL,AX,EAX}Jan Beulich1-0/+4
2021-03-30x86: adjust st(<N>) parsingJan Beulich1-0/+7
2021-03-29x86: move some opcode table entriesJan Beulich1-0/+10
2021-03-29x86: VPSADBW's source operands are also commutativeJan Beulich1-0/+6
2021-03-29x86: fold SSE2AVX and their base MMX/SSE templatesJan Beulich1-0/+7
2021-03-29x86: undo Prefix_0X<nn> use in opcode tableJan Beulich1-0/+8
2021-03-29x86: shrink some struct insn_template fieldsJan Beulich1-0/+6
2021-03-29x86: derive opcode encoding space attribute from base opcodeJan Beulich1-0/+10
2021-03-29TRUE/FALSE simplificationAlan Modra1-0/+21
2021-03-29opcodes int vs bfd_boolean fixesAlan Modra1-0/+5
2021-03-26x86-64: don't accept supposedly disabled MOVQ formsJan Beulich1-0/+6
2021-03-25[NIOS2] Fix disassembly of br.n instruction.Hafiz Abid Qadeer1-0/+5
2021-03-25x86: flag bad S/G insn operand combinationsJan Beulich1-0/+14
2021-03-25x86: flag as bad AVX512 insns with EVEX.z set but EVEX.aaa clearJan Beulich1-0/+5
2021-03-25x86: fix AMD Zen3 insnsJan Beulich1-0/+7
2021-03-25PR27647 PowerPC extended conditional branch mnemonicsAlan Modra1-0/+9
2021-03-24x86: derive opcode length from opcode valueJan Beulich1-0/+10
2021-03-24x86: derive mandatory prefix attribute from base opcodeJan Beulich1-0/+13
2021-03-24x86: don't use opcode_length to identify pseudo prefixesJan Beulich1-0/+9
2021-03-23x86: re-number PREFIX_0X<nn>Jan Beulich1-0/+6
2021-03-23x86: re-order two fields of struct insn_templateJan Beulich1-0/+6
2021-03-23x86: split opcode prefix and opcode space representationJan Beulich1-0/+14
2021-03-22Add startswith function and use it instead of CONST_STRNEQ.Martin Liska1-0/+18
2021-03-16RISC-V : Support bitmanip-0.93 ZBA/ZBB/ZBC instructionsKuan-Lin Chen1-0/+4
2021-03-12aarch64: Add few missing system registersPrzemyslaw Wirkus1-0/+5
2021-03-12Re: x86: correct decoding of nop/reserved space (0f18 ... 0x1f)Alan Modra1-0/+4
2021-03-11x86: re-order logic in OP_XMM()Jan Beulich1-0/+4
2021-03-11x86: drop a few redundant EVEX-related checksJan Beulich1-0/+7
2021-03-11x86: remove stray uses of xmmq_modeJan Beulich1-0/+5
2021-03-10x86/Intel: correct AVX512 S/G disassemblyJan Beulich1-0/+21
2021-03-10x86: re-arrange enumerator and table entry orderJan Beulich1-0/+21
2021-03-10x86: reuse further VEX entries for EVEXJan Beulich1-0/+19
2021-03-10x86: reuse VEX entries for EVEX vperm{q,pd}Jan Beulich1-0/+10
2021-03-10x86: re-arrange order of decode for various EVEX opcodesJan Beulich1-0/+67
2021-03-10x86: re-arrange order of decode for various mask reg opcodesJan Beulich1-0/+99
2021-03-10x86: re-arrange order of decode for various VEX opcodesJan Beulich1-0/+34
2021-03-10x86: re-arrange order of decode for various legacy opcodesJan Beulich1-0/+15
2021-03-10x86: correct decoding of nop/reserved space (0f18 ... 0x1f)Jan Beulich1-0/+16
2021-03-09x86: fold some prefix related attributes into a single oneJan Beulich1-0/+19
2021-03-09x86-64: make SYSEXIT handling similar to SYSRET'sJan Beulich1-0/+7
2021-03-03x86: infer operand count of templatesJan Beulich1-0/+7
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