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2020-08-11PowerPC CELL cctp*Alan Modra1-0/+4
2020-08-10[aarch64] GAS doesn't validate the architecture version for any tlbi register...Przemyslaw Wirkus1-0/+9
2020-08-10Implement missing powerpc mtspr and mfspr extended insnsAlan Modra1-0/+5
2020-08-10Implement missing powerpc extended mnemonicsAlan Modra1-0/+5
2020-08-10Prioritise mtfprd and mtvrd over mtvsrd in PowerPC disassemblyAlan Modra1-0/+5
2020-08-04Z8k: fix sout/soudb opcodes with direct addressChristian Groessler1-0/+7
2020-07-30x86: Add {disp16} pseudo prefixH.J. Lu1-0/+16
2020-07-29PR26279 Work around maybe-uninitialized warning in s390-mkopc.cAndreas Arnez1-0/+6
2020-07-24Updated German translation for the opcodes sub-directoryNick Clifton1-0/+4
2020-07-21Revert "x86: Don't display eiz with no scale"Jan Beulich1-0/+4
2020-07-15x86: Don't display eiz with no scaleH.J. Lu1-0/+6
2020-07-15x86: move putop() case labels to restore alphabetic sortingJan Beulich1-0/+4
2020-07-15x86: make PUSH/POP disassembly uniformJan Beulich1-0/+7
2020-07-15x86: avoid attaching suffixes to unambiguous insnsJan Beulich1-0/+14
2020-07-14x86-64: Zero-extend lower 32 bits displacement to 64 bitsH.J. Lu1-0/+6
2020-07-14arc: Detect usage of illegal double register pairsClaudiu Zissulescu1-0/+5
2020-07-14x86/Intel: debug registers are named DRnJan Beulich1-0/+4
2020-07-14x86: drop Rm and the 'L' macroJan Beulich1-0/+13
2020-07-14x86: drop Rdq, Rd, and MaskRJan Beulich1-0/+20
2020-07-14x86: simplify decode of opcodes valid only without any (embedded) prefixJan Beulich1-0/+19
2020-07-14x86: also use %BW / %DQ for kshift*Jan Beulich1-0/+18
2020-07-14x86: simplify decode of opcodes valid with (embedded) 66 prefix onlyJan Beulich1-0/+338
2020-07-14x86: drop further EVEX table entries that can be served by VEX onesJan Beulich1-0/+13
2020-07-14x86: drop need_vex_regJan Beulich1-0/+21
2020-07-14x86: drop Vex128 and Vex256Jan Beulich1-0/+17
2020-07-14x86: replace %LW by %DQJan Beulich1-0/+7
2020-07-14x86: merge/move logic determining the EVEX disp8 shiftJan Beulich1-0/+7
2020-07-14x86: extend %BW use to VP{COMPRESS,EXPAND}{B,W}Jan Beulich1-0/+13
2020-07-14x86-64: fix {,V}PCMPESTR{I,M} disassembly in Intel modeJan Beulich1-0/+14
2020-07-14x86: fold VCMP_Fixup() into CMP_Fixup()Jan Beulich1-0/+9
2020-07-14x86: don't disassemble MOVBE with two suffixesJan Beulich1-0/+6
2020-07-14x86: avoid attaching suffix to register-only CRC32Jan Beulich1-0/+5
2020-07-14x86-64: don't hide an empty but meaningless REX prefixJan Beulich1-0/+5
2020-07-14x86: drop dead code from OP_IMREG()Jan Beulich1-0/+8
2020-07-10x86: Add support for Intel AMX instructionsLili Cui1-0/+78
2020-07-08x86: various XOP insns lack L and/or W bit decodingJan Beulich1-0/+57
2020-07-08x86: FMA4 scalar insns ignore VEX.LJan Beulich1-0/+12
2020-07-08x86: re-work operand swapping for XOP shift/rotate insnsJan Beulich1-0/+8
2020-07-08x86: re-work operand handling for 5-operand XOP insnsJan Beulich1-0/+10
2020-07-08x86: re-work operand swapping for FMA4 and 4-operand XOP insnsJan Beulich1-0/+7
2020-07-07arc: Update vector instructions.Claudiu Zissulescu1-0/+8
2020-07-07x86: introduce %BW to avoid going through vex_w_table[]Jan Beulich1-0/+13
2020-07-06x86: adjust/correct VFRCZ{P,S}{S,D} decodingJan Beulich1-0/+12
2020-07-06x86: use %LW / %XW instead of going through vex_w_table[]Jan Beulich1-0/+14
2020-07-06x86: most VBROADCAST{F,I}{32,64}x* only accept memory operandsJan Beulich1-0/+26
2020-07-06x86: adjust/correct V*{F,I}{32x8,64x4}Jan Beulich1-0/+8
2020-07-06x86: drop EVEX table entries that can be made served by VEX onesJan Beulich1-0/+32
2020-07-06x86: AVX512 VPERM{D,Q,PS,PD} insns need to honor EVEX.L'LJan Beulich1-0/+11
2020-07-06x86: AVX512 extract/insert insns need to honor EVEX.L'LJan Beulich1-0/+13
2020-07-06x86: honor VEX.W for VCVT{PH2PS,PS2PH}Jan Beulich1-0/+14
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