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AgeCommit message (Expand)AuthorFilesLines
2020-01-30x86-64: honor vendor specifics for near RETJan Beulich1-0/+9
2020-01-30x86: drop further pointless/bogus DefaultSizeJan Beulich1-0/+8
2020-01-30ubsan: tic4x: left shift cannot be represented in type 'int'Alan Modra1-0/+4
2020-01-27x86-64: Properly encode and decode movsxdH.J. Lu1-0/+15
2020-01-27AArch64: Fix cfinv disassembly issuesTamar Christina1-0/+8
2020-01-21x86: improve handling of insns with ambiguous operand sizesJan Beulich1-0/+5
2020-01-21x86: VCVTNEPS2BF16{X,Y} should permit broadcastingJan Beulich1-0/+7
2020-01-20Updated translations for various binutils sub-directoriesNick Clifton1-0/+6
2020-01-20ubsan: hppa: negation of -2147483648Alan Modra1-0/+4
2020-01-20ubsan: arm: out of bounds array accessAlan Modra1-0/+4
2020-01-18Update version to 2.34.50. Regenerate configure and .pot files.Nick Clifton1-0/+5
2020-01-18Add markers for 2.34 branch to the NEWS files and ChangeLogs.Nick Clifton1-0/+4
2020-01-17Fix spelling errorsChristian Biesinger1-0/+4
2020-01-17x86: Add {vex} pseudo prefixH.J. Lu1-0/+5
2020-01-16[binutils][arm] PR25376 Change MVE into a CORE_HIGH featureAndre Vieira1-0/+9
2020-01-16x86: drop stale Vec_Imm4 related commentJan Beulich1-0/+4
2020-01-16x86: add a few more missing VexWIGJan Beulich1-0/+6
2020-01-16x86: VPEXTRQ/VPINSRQ are unavailable outside of 64-bit modeJan Beulich1-0/+8
2020-01-16tic4x disassembly static variablesAlan Modra1-0/+10
2020-01-14Fix various assembler testsuite failures for the Z80 target.Sergey Belyashov1-0/+6
2020-01-14ubsan: z8k: left shift cannot be represented in type 'int'Alan Modra1-0/+5
2020-01-13Add an option to objdump's disassembler to generate ascii art diagrams showin...Thomas Troeger1-0/+9
2020-01-13[ARC][committed] Code cleanup and improvements.Claudiu Zissulescu1-0/+4
2020-01-13[ARC] [COMMITTED] Change ACCL/ACCH reg name to generic.Claudiu Zissulescu1-0/+5
2020-01-13asan: ns32k: wild memory writeAlan Modra1-0/+5
2020-01-13ubsan: wasm32: signed integer overflowAlan Modra1-0/+7
2020-01-13score formattingAlan Modra1-0/+5
2020-01-13ubsan: score: left shift of negative valueAlan Modra1-0/+7
2020-01-13tic4x: sign extension using shiftsAlan Modra1-0/+4
2020-01-13ubsan: fr30: left shift of negative valueAlan Modra1-0/+4
2020-01-13ubsan: xgate: left shift of negative valueAlan Modra1-0/+5
2020-01-10ubsan: tilepro: signed integer overflowAlan Modra1-0/+5
2020-01-10ubsan: m10300: shift exponent -4Alan Modra1-0/+6
2020-01-09Fix the cast used to prevent compile time warning about an always false test.Nick Clifton1-0/+5
2020-01-09Fix compile time warnings about comparisons always being false.Sergey Belyashov1-0/+6
2020-01-09x86: SYSENTER/SYSEXIT are unavailable in 64-bit mode on AMDJan Beulich1-0/+11
2020-01-08ubsan: z8k: index 10 out of bounds for type 'unsigned int const[10]'Alan Modra1-0/+12
2020-01-07[ARC] Add finer details for LLOCK and SCONDShahab Vahedi1-0/+9
2020-01-06ubsan: m32c: left shift of negative valueAlan Modra1-0/+4
2020-01-06PR25344, z80 disassembler recursionAlan Modra1-0/+9
2020-01-04ubsan: m32r: left shift of negative valueAlan Modra1-0/+4
2020-01-04ubsan: cr16: left shift cannot be represented in type 'int'Alan Modra1-0/+4
2020-01-04ubsan: crx: left shift cannot be represented in type 'int'Alan Modra1-0/+4
2020-01-04ubsan: d30v: left shift cannot be represented in type 'int'Alan Modra1-0/+4
2020-01-03Arm64: correct address index operands for LD1RO{H,W,D}Jan Beulich1-3/+8
2020-01-03Arm64: correct {su,us}dot SIMD encodingsJan Beulich1-0/+5
2020-01-03Arm64: correct uzp{1,2} mnemonicsJan Beulich1-0/+6
2020-01-03Arm64: correct 64-bit element fmmla encodingJan Beulich1-0/+6
2020-01-02Add support for the GBZ80, Z180, and eZ80 variants of the Z80 architecure. A...Sergey Belyashov1-0/+4
2020-01-01Re: Update year range in copyright notice of binutils filesAlan Modra1-0/+4
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