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AgeCommit message (Expand)AuthorFilesLines
2018-03-08x86: fold AVX vcvtpd2ps memory formsJan Beulich1-0/+6
2018-03-07XCOFF disassemblerAlan Modra1-0/+9
2018-03-03opcodes error messagesAlan Modra1-0/+31
2018-03-01x86: Encode AVX256/AVX512 vpsub[bwdq] with VEX128/EVEX128H.J. Lu1-0/+6
2018-03-01Add missing translations to ALL_LINGUASAlan Modra1-0/+5
2018-02-27[ARM] Remove ARM_FEATURE_COPY macroThomas Preud'homme1-0/+5
2018-02-27x86: Add -O[2|s] assembler command-line optionsH.J. Lu1-0/+14
2018-02-26crx string overflow warningAlan Modra1-0/+5
2018-02-22RISC-V: Make disassebler work for --enable-targets=all config.Jim Wilson1-0/+4
2018-02-22x86: Add {rex} pseudo prefixH.J. Lu1-0/+5
2018-02-20MIPS16/opcodes: Free up `M' operand codeMaciej W. Rozycki1-0/+5
2018-02-19[ARM] Fix bxns maskThomas Preud'homme1-0/+4
2018-02-13Fix compile time warning messages from gcc version 8 about cast between incom...Nick Clifton1-0/+6
2018-02-13WebAssembly: Correct an `index' global shadowing error for pre-4.8 GCCMaciej W. Rozycki1-0/+5
2018-02-12MIPS: Fix encoding for MIPSr6 sigrie instruction.Henry Wong1-0/+4
2018-02-05Updated Brazillian portuguese and Russian translationNick Clifton1-0/+4
2018-01-23Enable Intel PCONFIG instruction.Igor Tsimbalist1-0/+11
2018-01-23Enable Intel WBNOINVD instruction.Igor Tsimbalist1-0/+11
2018-01-17RISC-V: Fix bug in prior addi/c.nop patch.Jim Wilson1-0/+4
2018-01-17Replace CET bit with IBT and SHSTK bits.Igor Tsimbalist1-0/+12
2018-01-16Update translations for various binutils components.Nick Clifton1-0/+5
2018-01-15RISC-V: Add support for addi that compresses to c.nop.Jim Wilson1-0/+5
2018-01-15Update Ukranian translations for bfd, binutils, gas, gold, ld and opcodesNick Clifton1-0/+4
2018-01-13Update pot filesNick Clifton1-0/+4
2018-01-13Bump version number to 2.30.51Nick Clifton1-0/+4
2018-01-13Add note about 2.30 branch creation to changelogsNick Clifton1-0/+4
2018-01-11Remove VL variants for 4FMAPS and 4VNNIW insns.Igor Tsimbalist1-0/+5
2018-01-10x86: fix Disp8 handling for scalar AVX512_4FMAPS insnsJan Beulich1-0/+5
2018-01-10x86: fix Disp8 handling for AVX512VL VPCMP*{B,W} variantsJan Beulich1-0/+10
2018-01-09RISC-V: Disassemble x0 based addresses as 0.Jim Wilson1-0/+5
2018-01-09[Arm] Add CSDB instructionJames Greenhalgh1-0/+5
2018-01-09Add support for the AArch64's CSDB instruction.James Greenhalgh1-0/+7
2018-01-08x86: Properly encode vmovd with 64-bit memeoryH.J. Lu1-0/+7
2018-01-05RISC-V: Print symbol address for jalr w/ zero offset.Jim Wilson1-0/+5
2018-01-03Update year range in copyright notice of binutils filesAlan Modra1-0/+4
2018-01-03ChangeLog rotationAlan Modra1-1965/+2
2018-01-02x86: partial revert of 10c17abdd0Jan Beulich1-0/+5
2017-12-20RISC-V: Add compressed instruction hints, and a few misc cleanups.Jim Wilson1-0/+11
2017-12-19Correct disassembly of dot product instructions.Tamar Christina1-0/+10
2017-12-19Add support for V_4B so we can properly reject it.Tamar Christina1-0/+5
2017-12-18x86: fold certain AVX and AVX2 templatesJan Beulich1-0/+38
2017-12-18x86: fold RegXMM/RegYMM/RegZMM into RegSIMDJan Beulich1-0/+18
2017-12-18x86: drop FloatReg and FloatAccJan Beulich1-0/+10
2017-12-18x86: replace Reg8, Reg16, Reg32, and Reg64Jan Beulich1-0/+20
2017-12-15Fix disassembly for PowerPCDimitar Dimitrov1-0/+5
2017-12-15x86: drop stray CheckRegSize usesJan Beulich1-0/+9
2017-12-13Add missing RISC-V fsrmi and fsflagsi instructions.Jim Wilson1-0/+5
2017-12-13This patch enables disassembler_needs_relocs for PRU. It is needed to print c...Dimitar Dimitrov1-0/+4
2017-12-11[Binutils][Objdump]Check symbol section information while search a mapping sy...Renlin Li1-0/+6
2017-12-03Fix "FAIL: VLE relocations 3"Alan Modra1-0/+4
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