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AgeCommit message (Expand)AuthorFilesLines
2016-09-21[AArch64] Print spaces after commas in addressesRichard Sandiford1-0/+6
2016-09-21[AArch64] Use "must" rather than "should" in error messagesRichard Sandiford1-0/+5
2016-09-21[AArch64] Add SVE condition codesRichard Sandiford1-0/+10
2016-09-21[AArch64][SVE 31/32] Add SVE instructionsRichard Sandiford1-0/+35
2016-09-21[AArch64][SVE 30/32] Add SVE instruction classesRichard Sandiford1-0/+12
2016-09-21[AArch64][SVE 29/32] Add new SVE core & FP register operandsRichard Sandiford1-0/+13
2016-09-21[AArch64][SVE 28/32] Add SVE FP immediate operandsRichard Sandiford1-0/+23
2016-09-21[AArch64][SVE 27/32] Add SVE integer immediate operandsRichard Sandiford1-0/+38
2016-09-21[AArch64][SVE 26/32] Add SVE MUL VL addressing modesRichard Sandiford1-0/+25
2016-09-21[AArch64][SVE 25/32] Add support for SVE addressing modesRichard Sandiford1-0/+42
2016-09-21[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALEDRichard Sandiford1-0/+22
2016-09-21[AArch64][SVE 23/32] Add SVE pattern and prfop operandsRichard Sandiford1-0/+16
2016-09-21[AArch64][SVE 22/32] Add qualifiers for merging and zeroing predicationRichard Sandiford1-0/+6
2016-09-21[AArch64][SVE 21/32] Add Zn and Pn registersRichard Sandiford1-0/+22
2016-09-21[AArch64][SVE 20/32] Add support for tied operandsRichard Sandiford1-0/+8
2016-09-21[AArch64][SVE 19/32] Refactor address-printing codeRichard Sandiford1-0/+9
2016-09-21[AArch64][SVE 18/32] Tidy definition of aarch64-opc.c:int_regRichard Sandiford1-0/+6
2016-09-21[AArch64][SVE 17/32] Add a prefix parameter to print_register_listRichard Sandiford1-0/+5
2016-09-21[AArch64][SVE 16/32] Use specific insert/extract methods for fpimmRichard Sandiford1-0/+12
2016-09-21[AArch64][SVE 15/32] Add {insert,extract}_all_fields helpersRichard Sandiford1-0/+8
2016-09-21[AArch64][SVE 14/32] Make aarch64_logical_immediate_p take an element sizeRichard Sandiford1-0/+9
2016-09-21[AArch64][SVE 13/32] Add an F_STRICT flagRichard Sandiford1-0/+4
2016-09-21[AArch64][SVE 02/32] Avoid hard-coded limit in indented_printRichard Sandiford1-0/+4
2016-09-16[ARC] Disassemble correctly extension instructions.Claudiu Zissulescu1-0/+4
2016-09-14Modify POWER9 support to match final ISA 3.0 documentation.Peter Bergner1-0/+16
2016-09-14Stop the ARC disassembler from seg-faulting if initialised without a BFD pres...Anton Kolesov1-0/+4
2016-09-12S/390: Add alternate processor names.Andreas Krebbel1-0/+4
2016-09-12S/390: Fix kmctr instruction type.Patrick Steuer1-0/+4
2016-09-07X86: Allow additional ISAs for IAMCU in assemblerH.J. Lu1-0/+5
2016-08-30Fixed issue with NULL pointer access on header var.Cupertino Miranda1-0/+4
2016-08-26opcodes, gas: fix mnemonic of sparc camellia_flJose E. Marchesi1-0/+5
2016-08-26Add missing ARMv8-M special registersThomas Preud'homme1-0/+6
2016-08-24X86: Add ptwrite instructionH.J. Lu1-0/+16
2016-08-24[ARC] C++ compatibility for arc-dis.hAnton Kolesov1-0/+4
2016-08-23[AArch64] Add V8_2_INSN macroRichard Sandiford1-0/+5
2016-08-23[AArch64] Make more use of CORE/FP/SIMD_INSNRichard Sandiford1-0/+5
2016-08-23[AArch64] Add OP parameter to aarch64-tbl.h macrosRichard Sandiford1-0/+5
2016-08-01 Fix some PowerPC VLE BFD issues and add some PowerPC VLE instructions.Andrew Jenner1-0/+10
2016-07-27MIPS/GAS: Implement microMIPS branch/jump compactionMaciej W. Rozycki1-0/+6
2016-07-27Begin implementing ARC NPS-400 Accelerator instructionsGraham Markall1-0/+19
2016-07-21Set BFD_VERSION to 2.27.51H.J. Lu1-0/+4
2016-07-20Add support to the ARC disassembler for selecting instruction classes.Claudiu Zissulescu1-0/+19
2016-07-13MIPS/opcodes: Address issues with NAL disassemblyMaciej W. Rozycki1-0/+5
2016-07-13opcodes,gas: support for the ldtxa SPARC instructions.Jose E. Marchesi1-0/+8
2016-07-08FT32: adjust disassembly opcode match fieldsjamesbowman1-0/+5
2016-07-01x86: allow suffix-less movzw and 64-bit movzbJan Beulich1-0/+7
2016-07-01x86: remove stray instruction attributesJan Beulich1-0/+15
2016-07-01x86/Intel: fix operand checking for MOVSDJan Beulich1-0/+5
2016-06-30Fix typo in commentYao Qi1-0/+4
2016-06-28[AArch64] Make register indices be full 64-bit valuesRichard Sandiford1-0/+7
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