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2020-12-10RISC-V: Add sext.[bh] and zext.[bhw] pseudo instructions.Nelson Chu1-0/+4
2020-12-10RISC-V: Dump CSR according to the elf privileged spec attributes.Nelson Chu1-0/+11
2020-12-10RISC-V: Control fence.i and csr instructions by zifencei and zicsr.Nelson Chu1-0/+5
2020-12-04IBM Z: Add risbgz and risbgnz extended mnemonicsAndreas Krebbel1-0/+7
2020-12-03IBM Z: Add support for HLASM extended mnemonicsAndreas Krebbel1-0/+4
2020-12-01RISC-V: Remove the unimplemented extensions.Nelson Chu1-0/+5
2020-12-01RISC-V: Add zifencei and prefixed h class extensions.Nelson Chu1-0/+4
2020-11-29x86: Do not dump DS/CS segment overrides for branch hintsBorislav Petkov1-0/+5
2020-11-16aarch64: Extract Condition flag manipulation feature from Armv8.4-APrzemyslaw Wirkus1-0/+7
2020-11-14x86: Ignore CS/DS/ES/SS segment-override prefixes in 64-bit modeBorislav Petkov1-0/+7
2020-11-11aarch64: Allow LS64 feature with Armv8.6Przemyslaw Wirkus1-0/+4
2020-11-09Add support for the LMBD (left-most bit detect) instruction to the PRU assemb...Spencer E. Olson1-0/+5
2020-11-09aarch64: Update LS64 feature with system registerPrzemyslaw Wirkus1-0/+4
2020-11-09aarch64: Limit Rt register number for LS64 load/store instructionsPrzemyslaw Wirkus1-0/+10
2020-11-06aarch64: Extract Pointer Authentication feature from Armv8.3-APrzemyslaw Wirkus1-0/+7
2020-11-04aarch64: Update feature RAS system registersPrzemyslaw Wirkus1-0/+5
2020-11-03[PATCH][GAS] aarch64: Add atomic 64-byte load/store instructions for Armv8.7Przemyslaw Wirkus1-0/+10
2020-11-03[PATCH] aarch64: Update missing ChangeLog for AArch64 commitsPrzemyslaw Wirkus1-0/+54
2020-10-26CSKY: Change plsl.u16 to plsl.16.Cooper Qu1-0/+4
2020-10-26CSKY: Fix and add some instructions for VDSPV1.Cooper Qu1-0/+8
2020-10-26Change avxvnni disassembler output from {vex3} to {vex}Cui,Lili1-0/+4
2020-10-22opcodes/po/es.po: Remove the duplicated entryH.J. Lu1-0/+4
2020-10-22Fix printf formatting errors where "0x" is used as a prefix for a decimal num...Dr. David Alan Gilbert1-0/+4
2020-10-20Add AMD znver3 processor supportGanesh Gopalasubramanian1-0/+13
2020-10-16Enhancement for avx-vnni patchCui,Lili1-0/+11
2020-10-14x86: Support Intel AVX VNNIH.J. Lu1-0/+27
2020-10-14x86: Add support for Intel HRESET instructionLili Cui1-0/+21
2020-10-14x86: Support Intel UINTRLili Cui1-0/+23
2020-10-14x86: Remove the prefix byte from non-VEX/EVEX base_opcodeH.J. Lu1-0/+10
2020-10-13x86: Rename VexOpcode to OpcodePrefixH.J. Lu1-0/+17
2020-10-05Fix spelling mistakesSamanta Navarro1-0/+6
2020-10-05x86-64: Always display suffix for %LQ in 64bitH.J. Lu1-0/+5
2020-10-05x86: Clear modrm if not neededH.J. Lu1-0/+7
2020-09-28This patch introduces ETMv4 (Embedded Trace Macrocell) system registers for t...Przemyslaw Wirkus1-3/+20
2020-09-28This patch introduces ETE (Embedded Trace Extension) system registers for the...Przemyslaw Wirkus1-0/+4
2020-09-28This patch introduces TRBE (Trace Buffer Extension) system registers for the ...Przemyslaw Wirkus1-0/+5
2020-09-26ubsan: opcodes/csky-opc.h:929 shift exponent 536870912Alan Modra1-10/+18
2020-09-25Put together MOD_VEX_0F38* in i386-dis.c,Cui,Lili1-0/+5
2020-09-24csky/opcodes: enclose if body in curly bracesAndrew Burgess1-0/+5
2020-09-24Add support for Intel TDX instructions.Cui,Lili1-0/+18
2020-09-23CSKY: Add objdump option -M abi-names.Cooper Qu1-0/+34
2020-09-23Enable support to Intel Keylocker instructionsTerry Guo1-0/+21
2020-09-21rx-dis.c:103:3: suspicious concatenation of string literalsAlan Modra1-0/+8
2020-09-18bpf: xBPF SDIV, SMOD instructionsDavid Faust1-0/+7
2020-09-17opcodes/csky: return the default disassembler when there is no bfdAndrew Burgess1-0/+5
2020-09-16Tidy elf_symbol_fromAlan Modra1-0/+4
2020-09-10Stop symbols generated by the annobin gcc plugin from breaking the disassembl...Nick Clifton1-0/+7
2020-09-10CSKY: Add L2Cache instructions for CK860.Cooper Qu1-0/+6
2020-09-10Fix compile time warnings when building for the CSKY target on a 32-bit host.Nick Clifton1-0/+5
2020-09-10sprintf arg overlaps destinationAlan Modra1-0/+4
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