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2018-09-15x86: Set Vex=1 on VEX.128 only vmovqH.J. Lu1-0/+8
2018-09-14x86: Support VEX/EVEX WIG encodingH.J. Lu1-0/+7
2018-09-14x86: Handle unsupported static rounding in vcvt[u]si2sd in 32-bit modeH.J. Lu1-0/+9
2018-09-14x86: Properly decode EVEX.W in vcvt[u]si2s[sd] in 32-bit modeH.J. Lu1-0/+11
2018-09-14i386: Reformat OP_E_memoryH.J. Lu1-0/+4
2018-09-14x86: fold CRC32 templatesJan Beulich1-0/+5
2018-09-13i386: Update VexW field for VEX instructionsH.J. Lu1-0/+8
2018-09-13x86: drop bogus IgnoreSize from a few further insnsJan Beulich1-0/+9
2018-09-13x86: drop bogus IgnoreSize from AVX512_4* insnsJan Beulich1-0/+6
2018-09-13x86: drop bogus IgnoreSize from AVX512DQ insnsJan Beulich1-0/+6
2018-09-13x86: drop bogus IgnoreSize from AVX512BW insnsJan Beulich1-0/+6
2018-09-13x86: drop bogus IgnoreSize from AVX512VL insnsJan Beulich1-0/+6
2018-09-13x86: drop bogus IgnoreSize from AVX512ER insnsJan Beulich1-0/+6
2018-09-13x86: drop bogus IgnoreSize from AVX512F insnsJan Beulich1-0/+6
2018-09-13x86: drop bogus IgnoreSize from SHA insnsJan Beulich1-0/+5
2018-09-13x86: drop bogus IgnoreSize from XOP and SSE4a insnsJan Beulich1-0/+5
2018-09-13x86: drop bogus IgnoreSize from AVX2 insnsJan Beulich1-0/+6
2018-09-13x86: drop bogus IgnoreSize from AVX insnsJan Beulich1-0/+6
2018-09-13x86: drop bogus IgnoreSize from GNFI insnsJan Beulich1-0/+5
2018-09-13x86: drop bogus IgnoreSize from PCLMUL/VPCLMUL insnsJan Beulich1-0/+5
2018-09-13x86: drop bogus IgnoreSize from AES/VAES insnsJan Beulich1-0/+5
2018-09-13x86: drop bogus IgnoreSize from SSE4.2 insnsJan Beulich1-0/+6
2018-09-13x86: drop bogus IgnoreSize from SSE4.1 insnsJan Beulich1-0/+6
2018-09-13x86: drop bogus IgnoreSize from SSSE3 insnsJan Beulich1-0/+6
2018-09-13x86: drop bogus IgnoreSize from SSE3 insnsJan Beulich1-0/+5
2018-09-13x86: drop bogus IgnoreSize from SSE2 insnsJan Beulich1-0/+5
2018-09-13x86: drop bogus IgnoreSize from SSE insnsJan Beulich1-0/+5
2018-09-13x86: drop unnecessary {,No}Rex64Jan Beulich1-0/+6
2018-09-13x86: also allow D on 3-operand insnsJan Beulich1-0/+6
2018-09-13x86: use D attribute also for SIMD templatesJan Beulich1-0/+12
2018-09-13x86-64: bndmk, bndldx, and bndstx don't allow RIP-relative addressingJan Beulich1-0/+7
2018-09-08S12Z: Make disassebler work for --enable-targets=all config.John Darrington1-0/+4
2018-08-31RISC-V: Correct the requirement of compressed floating point instructionsJim Wilson1-0/+5
2018-08-30RISC-V: Allow instruction require more than one extensionJim Wilson1-0/+6
2018-08-29sparc/leon: add support for partial write psr instructionMartin Aberg1-0/+5
2018-08-29[MIPS] Add Loongson 2K1000 proccessor support.Chenghua Xu1-0/+4
2018-08-29[MIPS] Add Loongson 3A2000/3A3000 proccessor support.Chenghua Xu1-0/+4
2018-08-29[MIPS] Add Loongson 3A1000 proccessor support.Chenghua Xu1-0/+6
2018-08-29[MIPS/GAS] Add Loongson EXT2 Instructions support.Chenghua Xu1-0/+8
2018-08-29[MIPS/GAS] Split Loongson EXT Instructions from loongson3a.Chenghua Xu1-0/+11
2018-08-29[MIPS/GAS] Split Loongson CAM Instructions from loongson3aChenghua Xu1-0/+10
2018-08-21Use operand->extract to provide defaults for optional PowerPC operandsAlan Modra1-0/+16
2018-08-21Fix s12z test regexpsAlan Modra1-4/+3
2018-08-20Tidy bit twiddlingAlan Modra1-6/+11
2018-08-18Opcodes: (BRCLR / BRSET) Disassemble reserved codes instead of aborting.John Darrington1-0/+6
2018-08-18S12Z: Move opcode header to public include directory.John Darrington1-0/+4
2018-08-14x86-64: Display eiz for address with the addr32 prefixH.J. Lu1-0/+6
2018-08-11x86: Add CpuCMOV and CpuFXSRH.J. Lu1-0/+11
2018-08-06[ARC] Update handling AUX-registers.claziss1-0/+4
2018-08-06x86: fold RegEip/RegRip and RegEiz/RegRizJan Beulich1-0/+11
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