| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2018-11-12 | [BINUTILS, AARCH64, 3/8] Add Pointer Arithmetic instructions in Memory Taggin... | Sudakshina Das | 1 | -0/+7 |
| 2018-11-12 | [BINUTILS, AARCH64, 2/8] Add Tag generation instructions in Memory Tagging Ex... | Sudakshina Das | 1 | -0/+17 |
| 2018-11-12 | [BINUTILS, AARCH64, 1/8] Add support for Memory Tagging Extension for ARMv8.5-A | Sudakshina Das | 1 | -0/+5 |
| 2018-11-06 | [BINUTILS, ARM] Add Armv8.5-A to select_arm_features and update macros. | Sudakshina Das | 1 | -0/+5 |
| 2018-11-06 | PowerPC instruction mask checks | Alan Modra | 1 | -0/+14 |
| 2018-11-06 | x86: correctly handle VPBROADCASTD with EVEX.W set outside of 64-bit mode | Jan Beulich | 1 | -0/+5 |
| 2018-11-06 | x86: correctly handle VMOVD with EVEX.W set outside of 64-bit mode | Jan Beulich | 1 | -0/+6 |
| 2018-11-06 | x86: correctly handle KMOVD with VEX.W set outside of 64-bit mode | Jan Beulich | 1 | -0/+9 |
| 2018-11-06 | x86: adjust {,E}VEX.W handling for PEXTR* / PINSR* | Jan Beulich | 1 | -0/+15 |
| 2018-11-06 | x86: adjust {,E}VEX.W handling outside of 64-bit mode | Jan Beulich | 1 | -0/+7 |
| 2018-11-06 | x86: fix various non-LIG templates | Jan Beulich | 1 | -0/+10 |
| 2018-11-06 | x86: allow {store} to select alternative {,}PEXTRW encoding | Jan Beulich | 1 | -0/+6 |
| 2018-11-06 | x86: add more VexWIG | Jan Beulich | 1 | -0/+8 |
| 2018-11-06 | x86: XOP VPHADD* / VPHSUB* are VEX.W0 | Jan Beulich | 1 | -0/+6 |
| 2018-10-22 | S12Z: Disassembly: Fallback to show the address if the symbol table is empty. | John Darrington | 1 | -0/+5 |
| 2018-10-19 | Arm: Fix disassembler crashing on -b binary when thumb file and thumb not for... | Tamar Christina | 1 | -0/+6 |
| 2018-10-16 | AArch64: Fix error checking for SIMD udot (by element) | Matthew Malcomson | 1 | -0/+5 |
| 2018-10-10 | x86: fold Size{16,32,64} template attributes | Jan Beulich | 1 | -0/+12 |
| 2018-10-09 | [PATCH, BINUTULS, AARCH64, 9/9] Add SSBS to MSR/MRS | Sudakshina Das | 1 | -0/+9 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 8/9] Add SCXTNUM_ELx and ID_PFR2_EL1 system registers | Sudakshina Das | 1 | -0/+6 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 7/9] Add BTI instruction | Sudakshina Das | 1 | -0/+18 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 6/9] Add Random number instructions | Sudakshina Das | 1 | -0/+6 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 5/9] Add DC CVADP instruction | Sudakshina Das | 1 | -0/+5 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 4/9] Add Execution and Data Restriction instructions | Sudakshina Das | 1 | -0/+16 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 3/9] Add instruction SB for ARMv8.5-A | Sudakshina Das | 1 | -0/+9 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 2/9] Add Data procoessing instructions for ARMv8.5-A | Sudakshina Das | 1 | -0/+11 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 1/9] Add -march=armv8.5-a and related internal fea... | Sudakshina Das | 1 | -0/+5 |
| 2018-10-08 | AArch64: Replace C initializers with memset | Tamar Christina | 1 | -0/+4 |
| 2018-10-05 | x86: Add Intel ENCLV to assembler and disassembler | H.J. Lu | 1 | -0/+6 |
| 2018-10-05 | [Arm, 2/3] Add instruction SB for AArch32 | Sudakshina Das | 1 | -0/+5 |
| 2018-10-05 | or1k: Add the l.muld, l.muldu, l.macu, l.msbu insns | Richard Henderson | 1 | -0/+9 |
| 2018-10-05 | or1k: Add the l.adrp insn and supporting relocations | Stafford Horne | 1 | -0/+11 |
| 2018-10-05 | or1k: Add relocations for high-signed and low-stores | Richard Henderson | 1 | -0/+4 |
| 2018-10-03 | AArch64: Constraint disassembler and assembler changes. | Tamar Christina | 1 | -0/+9 |
| 2018-10-03 | AArch64: Add SVE constraints verifier. | Tamar Christina | 1 | -0/+6 |
| 2018-10-03 | AArch64: Refactor verifiers to make more general. | Tamar Christina | 1 | -0/+5 |
| 2018-10-03 | AArch64: Refactor err_type. | Tamar Christina | 1 | -0/+5 |
| 2018-10-03 | AArch64: Wire through instr_sequence | Tamar Christina | 1 | -0/+5 |
| 2018-10-03 | AArch64: Mark sve instructions that require MOVPRFX constraints | Tamar Christina | 1 | -0/+20 |
| 2018-10-02 | RISC-V: Add fence.tso instruction | Palmer Dabbelt | 1 | -0/+4 |
| 2018-09-23 | Fix incorrect extraction of signed constants in nios2 disassembler. | Sandra Loosemore | 1 | -0/+6 |
| 2018-09-21 | csky-opc.h: Initialize fields of last array elements | Simon Marchi | 1 | -0/+10 |
| 2018-09-20 | ARC: Fix build errors with large constants and C89 | Maciej W. Rozycki | 1 | -0/+4 |
| 2018-09-20 | Andes Technology has good news for you, we plan to update the nds32 port of b... | Nick Clifton | 1 | -0/+40 |
| 2018-09-17 | RISC-V: bge[u] should get higher priority than ble[u]. | Jim Wilson | 1 | -0/+4 |
| 2018-09-17 | x86: Set EVex=2 on EVEX.128 only vmovd and vmovq | H.J. Lu | 1 | -0/+20 |
| 2018-09-17 | x86: Set Vex=1 on VEX.128 only vmovd and vmovq | H.J. Lu | 1 | -0/+8 |
| 2018-09-17 | x86: Update disassembler for VexWIG | H.J. Lu | 1 | -0/+387 |
| 2018-09-17 | x86: Replace VexW=3 with VexWIG | H.J. Lu | 1 | -0/+5 |
| 2018-09-15 | x86: Set VexW=3 on AVX vrsqrtss | H.J. Lu | 1 | -0/+5 |
