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2016-08-30Fixed issue with NULL pointer access on header var.Cupertino Miranda1-0/+4
2016-08-26opcodes, gas: fix mnemonic of sparc camellia_flJose E. Marchesi1-0/+5
2016-08-26Add missing ARMv8-M special registersThomas Preud'homme1-0/+6
2016-08-24X86: Add ptwrite instructionH.J. Lu1-0/+16
2016-08-24[ARC] C++ compatibility for arc-dis.hAnton Kolesov1-0/+4
2016-08-23[AArch64] Add V8_2_INSN macroRichard Sandiford1-0/+5
2016-08-23[AArch64] Make more use of CORE/FP/SIMD_INSNRichard Sandiford1-0/+5
2016-08-23[AArch64] Add OP parameter to aarch64-tbl.h macrosRichard Sandiford1-0/+5
2016-08-01 Fix some PowerPC VLE BFD issues and add some PowerPC VLE instructions.Andrew Jenner1-0/+10
2016-07-27MIPS/GAS: Implement microMIPS branch/jump compactionMaciej W. Rozycki1-0/+6
2016-07-27Begin implementing ARC NPS-400 Accelerator instructionsGraham Markall1-0/+19
2016-07-21Set BFD_VERSION to 2.27.51H.J. Lu1-0/+4
2016-07-20Add support to the ARC disassembler for selecting instruction classes.Claudiu Zissulescu1-0/+19
2016-07-13MIPS/opcodes: Address issues with NAL disassemblyMaciej W. Rozycki1-0/+5
2016-07-13opcodes,gas: support for the ldtxa SPARC instructions.Jose E. Marchesi1-0/+8
2016-07-08FT32: adjust disassembly opcode match fieldsjamesbowman1-0/+5
2016-07-01x86: allow suffix-less movzw and 64-bit movzbJan Beulich1-0/+7
2016-07-01x86: remove stray instruction attributesJan Beulich1-0/+15
2016-07-01x86/Intel: fix operand checking for MOVSDJan Beulich1-0/+5
2016-06-30Fix typo in commentYao Qi1-0/+4
2016-06-28[AArch64] Make register indices be full 64-bit valuesRichard Sandiford1-0/+7
2016-06-25remove a few sentinalsTrevor Saunders1-0/+5
2016-06-23[ARC] Misc minor edits/fixesGraham Markall1-0/+5
2016-06-22Add support for yet some more new ISA 3.0 instructions.Peter Bergner1-0/+10
2016-06-22addmore extern CTrevor Saunders1-0/+4
2016-06-21Arc assembler: Convert nps400 from a machine type to an extension.Graham Markall1-0/+10
2016-06-17opcodes,gas: sparc: fix rdasr,wrasr,rdpr,wrpr,rdhpr,wrhpr insns.Jose E. Marchesi1-0/+16
2016-06-17opcodes,gas: adjust sparc insns and make GAS aware of itJose E. Marchesi1-0/+5
2016-06-17bfd,opcodes: sparc: new opcode v9{c,d,e,v,m} architectures and bfd machine nu...Jose E. Marchesi1-0/+25
2016-06-15Fix simple gas testsuite failures.Nick Clifton1-0/+6
2016-06-15opcodes/arc: Fix extract for some add_s instructionsAndrew Burgess1-0/+4
2016-06-14opcode/gas: Fix incorrect dates on ChangeLog entriesGraham Markall1-3/+3
2016-06-14[ARC] Add ldbit for npsGraham Markall1-0/+5
2016-06-14[ARC] Add deep packet inspection instructions for npsGraham Markall1-0/+6
2016-06-14[ARC] Add arithmetic and logic instructions for npsGraham Markall1-0/+25
2016-06-10S/390: Dump unknown instructions according to their length.Andreas Krebbel1-0/+10
2016-06-09Print symbol names in comments for LDS/STS disassembly.Denis Chertykov1-0/+5
2016-06-07PowerPC VLEAlan Modra1-0/+11
2016-06-07[ARM] Add command line option for RAS extension.Matthew Wahab1-0/+5
2016-06-03Re-add support for lbarx, lharx, stbcx. and sthcx. insns back to the E6500 cpu.Peter Bergner1-0/+6
2016-06-03Handle indirect branches for AMD64 and Intel64H.J. Lu1-0/+14
2016-06-02Add support for 48 and 64 bit ARC instructions.Andrew Burgess1-0/+33
2016-06-01add more extern CTrevor Saunders1-0/+5
2016-06-01Add support for some variants of the ARC nps400 rflt instruction.Graham Markall1-0/+5
2016-05-31sh: make constant unsigned to avoid narrowingTrevor Saunders1-0/+5
2016-05-29Add missing ChangeLog entriesH.J. Lu1-0/+10
2016-05-27Update x86 CPU_XXX_FLAGS handlingH.J. Lu1-0/+32
2016-05-27Replace CpuAMD64/CpuIntel64 with AMD64/Intel64H.J. Lu1-0/+18
2016-05-27Correct CpuMax in i386-opc.hH.J. Lu1-0/+7
2016-05-27Improve the MSP430 disassembler's handling of memory read errors.Nick Clifton1-0/+14
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