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AgeCommit message (Expand)AuthorFilesLines
2017-02-24x86: also correctly support TEST opcode aliasesJan Beulich1-0/+4
2017-02-23opcodes,gas: associate SPARC ASIs with an architecture level.Sheldon Lobo1-0/+7
2017-02-23x86: drop stray VEX opcode 82 referencesJan Beulich1-0/+5
2017-02-22aarch64: actually copy first operand in convert_bfc_to_bfm()Jan Beulich1-0/+5
2017-02-15Add SFENCE.VMA instructionAndrew Waterman1-0/+5
2017-02-15[AArch64] Add SVE system registersRichard Sandiford1-0/+5
2017-02-15[ARC] Fix assembler relaxation.Claudiu Zissulescu1-0/+16
2017-02-15Distinguish some of the registers different on ARC700 and HS38 cpusVineet Gupta1-0/+5
2017-02-14PowerPC register expression checksAlan Modra1-0/+6
2017-02-11Fix use after free in cgen instruction lookupAlan Modra1-0/+7
2017-02-10POWER9 add scv/rfscv instruction supportNicholas Piggin1-0/+4
2017-02-03Fix compile time warning messages when compiling binutils with gcc 7.0.1.Nick Clifton1-0/+8
2017-01-27Fix disassembling of TIC6X parallel instructions where the previous fetch pac...Alexis Deruell1-0/+7
2017-01-25Clarify that include/opcode/ files are part of GNU opcodesDimitar Dimitrov1-0/+4
2017-01-20Updated Irish translation for the opcodes library.Nick Clifton1-0/+4
2017-01-18[ARM] Fix the decoding of indexed element VCMLA instructionSzabolcs Nagy1-0/+4
2017-01-13Return -1 on memory error in print_insn_m68kYao Qi1-0/+7
2017-01-13Remove magic numbers in m68k-dis.c:print_insn_argYao Qi1-0/+16
2017-01-12Enable Intel AVX512_VPOPCNTDQ instructionsIgor Tsimbalist1-0/+13
2017-01-12Return -1 on memory error in print_insn_msp430Yao Qi1-0/+10
2017-01-05Prevent an abort in the FRV disassembler if the target bfd name is unknown.Nick Clifton1-0/+8
2017-01-04[AArch64] Add separate feature flag for weaker release consistent load insnsSzabolcs Nagy1-0/+5
2017-01-03Add support for the Q extension to the RISCV ISA.Kito Cheng1-0/+6
2017-01-03Add fall through comment.Dilyan Palauzov1-0/+4
2017-01-03Add new Serbian translation for the opcodes library.Nick Clifton1-0/+6
2017-01-02Regen opcodes cgen filesAlan Modra1-0/+29
2017-01-02Update year range in copyright notice of all files.Alan Modra1-0/+4
2017-01-02ChangeLog rotationAlan Modra1-2167/+2
2016-12-31Fix riscv breakageAlan Modra1-0/+5
2016-12-31PRU Opcode PortDimitar Dimitrov1-0/+10
2016-12-29Return 'int' rather than 'unsigned short' in avrdis_opcodeYao Qi1-0/+8
2016-12-28Check bfd support for bfd_mips_elf_get_abiflags in mips make ruleAlan Modra1-0/+11
2016-12-23MIPS16: Add ASMACRO instruction supportMaciej W. Rozycki1-0/+6
2016-12-23MIPS16: Simplify extended operand handlingMaciej W. Rozycki1-0/+7
2016-12-23MIPS16: Reassign `0' and `4' operand codesMaciej W. Rozycki1-0/+6
2016-12-23MIPS16: Handle non-extensible instructions correctlyMaciej W. Rozycki1-0/+15
2016-12-23MIPS16: Remove "extended" BREAK/SDBBP handlingMaciej W. Rozycki1-0/+5
2016-12-23MIPS16/GAS: Disallow EXTEND delay-slot schedulingMaciej W. Rozycki1-0/+5
2016-12-23opcodes: Use autoconf to check for `bfd_mips_elf_get_abiflags' in BFDMaciej W. Rozycki1-0/+12
2016-12-23Bump version to 2.28.51Tristan Gingold1-0/+4
2016-12-23Regenerate pot files.Tristan Gingold1-0/+4
2016-12-22ChangeLog formatting fixesAlan Modra1-1/+1
2016-12-22Avoid creating symbol table entries for registersAndrew Waterman1-0/+4
2016-12-20MIPS16/opcodes: Respect ISA and ASE in disassemblyMaciej W. Rozycki1-0/+7
2016-12-20MIPS16: Switch to 32-bit opcode table interpretationMaciej W. Rozycki1-0/+11
2016-12-20MIPS16/opcodes: Correct 64-bit macros' ISA membershipMaciej W. Rozycki1-0/+6
2016-12-20MIPS16/opcodes: Correct I64/SDRASP opcode's ISA membershipMaciej W. Rozycki1-0/+6
2016-12-20Correct assembler mnemonic for RISC-V aqrl AMOsAndrew Waterman1-0/+5
2016-12-20Fix disassembly of RISC-V CSR instructions under -Mno-aliasesAndrew Waterman1-0/+5
2016-12-20Add canonical JALR for RISC-VAndrew Waterman1-0/+5
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