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AgeCommit message (Expand)AuthorFilesLines
2017-06-19Prevent address violation when attempting to disassemble a corrupt score binary.Nick Clifton1-0/+5
2017-06-17Regen rx-decode.cAlan Modra1-0/+4
2017-06-15i386-dis: Check valid bnd registerH.J. Lu1-0/+6
2017-06-15Prevent address violation problem when disassembling corrupt aarch64 binary.Nick Clifton1-0/+6
2017-06-15Fix address violation when disassembling a corrupt RL78 binary.Nick Clifton1-0/+9
2017-06-15Prevent invalid array accesses when disassembling a corrupt bfin binary.Nick Clifton1-0/+8
2017-06-14Fix seg-fault when trying to disassemble a corrupt score binary.Nick Clifton1-0/+5
2017-06-14Don't use print_insn_XXX in GDBYao Qi1-0/+13
2017-06-14Fix address violation problems when disassembling a corrupt RX binary.Nick Clifton1-0/+9
2017-06-14[opcodes][arm] Remove bogus entry added by accident in former patchAndre Vieira1-0/+4
2017-05-30[ARC] Allow CPU to be enforced via disassemble_info optionsAnton Kolesov1-0/+9
2017-05-24Move print_insn_XXX to an opcodes internal headerYao Qi1-0/+28
2017-05-24Use disassemble.c:disassembler select rl78 disassemblerYao Qi1-0/+5
2017-05-24Refactor disassembler selectionYao Qi1-0/+5
2017-05-22x86: Add NOTRACK prefix supportH.J. Lu1-0/+16
2017-05-19binutils: support for the SPARC M8 processorJose E. Marchesi1-0/+37
2017-05-18Don't compare boolean values against TRUE or FALSEAlan Modra1-0/+7
2017-05-15MIPS16e2: Add MIPS16e2 ASE supportMaciej W. Rozycki1-0/+28
2017-05-15MIPS/opcodes: Remove an incorrect MT ASE reference in MFC0/MTC0 decodingMaciej W. Rozycki1-0/+5
2017-05-12MIPS16/opcodes: Make the handling of BREAK and SDBBP consistentMaciej W. Rozycki1-0/+6
2017-05-12MIPS/opcodes: Mark descriptive SYNC mnemonics as aliasesMaciej W. Rozycki1-0/+8
2017-05-10[ARC] Object attributes.Claudiu Zissulescu1-0/+7
2017-05-04RISC-V: Fix disassemble for c.li, c.andi and c.addiwKito Cheng1-0/+4
2017-05-02RISC-V: Change CALL macro to use ra as the temporary address registerMichael Clark1-0/+5
2017-05-02MIPS16/opcodes: Keep the LSB of PC-relative offsets in disassemblyMaciej W. Rozycki1-0/+5
2017-05-02Fix value in comment of disassembled ARM type A opcodes.Bernd Edlinger1-0/+4
2017-04-25[ARC] Enhance enter/leave mnemonics.Claudiu Zissulescu1-0/+7
2017-04-25[ARC] Prefer NOP instead of MOV 0,0Claudiu Zissulescu1-0/+4
2017-04-25MIPS16/opcodes: Add `-M no-aliases' disassembler option help textMaciej W. Rozycki1-0/+5
2017-04-25MIPS16/opcodes: Annotate instruction aliasesMaciej W. Rozycki1-0/+6
2017-04-24Fix snafu in aarch64 opcodes debugging statement.Tamar Christina1-0/+5
2017-04-22PowerPC VLE insn set additionsAlan Modra1-0/+8
2017-04-21opcodes: mark SPARC RETT instructions as v6notv9.Jose E. Marchesi1-0/+4
2017-04-21Fix detection of illegal AArch64 opcodes that resemble LD1R, LD2R, LD3R and L...Nick Clifton1-0/+6
2017-04-13Regen cgen filesAlan Modra1-0/+16
2017-04-11Reorder PPC_OPCODE_* and set PPC_OPCODE_TMR for e6500Alan Modra1-1/+3
2017-04-11Bye bye PPC_OPCODE_HTM and -mhtmAlan Modra1-2/+3
2017-04-11Bye Bye PPC_OPCODE_VSX3Alan Modra1-1/+4
2017-04-11Bye bye PPC_OPCODE_ALTIVEC2Alan Modra1-0/+6
2017-04-10Tidy ppc476 opcodesAlan Modra1-0/+7
2017-04-10WebAssembly disassembler supportPip Cet1-0/+5
2017-04-07Remove E6500 insns from PPC_OPCODE_ALTIVEC2Alan Modra1-0/+8
2017-04-06Add support for disassembling WebAssembly opcodes.Pip Cet1-0/+11
2017-04-05-Wwrite-strings: Constify struct disassemble_info's disassembler_options fieldPedro Alves1-0/+7
2017-04-04RISC-V: Resurrect GP-relative disassembly hintsPalmer Dabbelt1-0/+5
2017-03-30Add support for the WebAssembly file format and the wasm32 ELF conversion to ...Pip Cet1-0/+6
2017-03-29opcodes: sparc: support missing SPARC ASIs from UA2005, UA2007, OSA2011, & OS...Jose E. Marchesi1-0/+6
2017-03-29PowerPC -Mraw disassemblyAlan Modra1-0/+9
2017-03-27PR21303, objdump doesn't show e200z4 insnsAlan Modra1-0/+6
2017-03-27Implement ARC NPS-400 Ultra Ip and Miscellaneous instructions.Rinat Zelig1-0/+10
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