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AgeCommit message (Expand)AuthorFilesLines
2021-06-03PR1202, mcore disassembler: wrong address looptAlan Modra1-0/+6
2021-06-02arc: Construct disassembler options dynamicallyShahab Vahedi1-0/+8
2021-05-29PowerPC table driven -Mraw disassemblyAlan Modra1-0/+15
2021-05-29MIPS/opcodes: Reorder legacy COP0, COP2, COP3 opcode instructionsMaciej W. Rozycki1-0/+5
2021-05-29MIPS/opcodes: Accurately record coprocessor opcode CPU/ISA membershipMaciej W. Rozycki1-0/+10
2021-05-29MIPS/opcodes: Remove DMFC3 and DMTC3 instructionsMaciej W. Rozycki1-0/+5
2021-05-29MIPS/opcodes: Disassemble the RFE instructionMaciej W. Rozycki1-0/+5
2021-05-29MIPS/opcodes: Add legacy CP1 control register namesMaciej W. Rozycki1-0/+10
2021-05-29MIPS/opcodes: Do not use CP0 register names for control registersMaciej W. Rozycki1-0/+14
2021-05-29MIPS/opcodes: Add TX39 CP0 register namesMaciej W. Rozycki1-0/+6
2021-05-29MIPS/opcodes: Free up redundant `g' operand codeMaciej W. Rozycki1-0/+6
2021-05-29microMIPS/opcodes: Refer FPRs rather than FCRs with DMTC1Maciej W. Rozycki1-0/+5
2021-05-27PowerPC: Add new xxmr and xxlnot extended mnemonicsPeter Bergner1-0/+4
2021-05-25Regen cris filesAlan Modra1-0/+7
2021-05-24opcodes: cris: move desc & opc files from sim/Mike Frysinger1-0/+11
2021-05-18RISC-V: PR27814, Objdump crashes when disassembling a non-ELF RISC-V binary.Job Noorman1-0/+6
2021-05-17arm: Fix bugs with MVE vmov from two GPRs to vector lanesAlex Coplan1-0/+9
2021-05-11Fix an illegal memory access when attempting to disassemble a corrupt TIC30 b...Nick Clifton1-0/+6
2021-05-06or1k: Implement relocation R_OR1K_GOT_AHI16 for gotha()Stafford Horne1-0/+5
2021-05-01opcodes: xtensa: support branch visualizationMax Filippov1-0/+5
2021-04-26x86: optimize LEAJan Beulich1-0/+5
2021-04-23opcodes: xtensa: display loaded literal valueMax Filippov1-0/+5
2021-04-23opcodes: xtensa: improve literal outputMax Filippov1-0/+5
2021-04-19aarch64: New instructions for maintenance of GPT entries cached in a TLBPrzemyslaw Wirkus1-0/+5
2021-04-19aarch64: Add new data cache maintenance operationsPrzemyslaw Wirkus1-0/+5
2021-04-19arm64: add two initializersJan Beulich1-0/+6
2021-04-16aarch64: Define RME system registersPrzemyslaw Wirkus1-0/+4
2021-04-16Update the ChangeLog, and add the missing entries.Nelson Chu1-0/+5
2021-04-13ENABLE_CHECKING in bfd, opcodes, binutils, ldAlan Modra1-0/+6
2021-04-09AArch64: Fix Atomic LD64/ST64 classification.Tejas Belagod1-0/+5
2021-04-09PowerPC disassembly of pcrel referencesAlan Modra1-0/+12
2021-04-08PR27684, PowerPC missing mfsprg0 and othersAlan Modra1-0/+5
2021-04-08PR27676, PowerPC missing extended dcbt, dcbtst mnemonicsAlan Modra1-0/+8
2021-04-06Return symbol from symbol_at_address_funcAlan Modra1-0/+6
2021-04-05C99 opcodes configuryAlan Modra1-0/+12
2021-04-01Remove strneq macro and use startswith.Martin Liska1-0/+8
2021-04-01PR27675, PowerPC missing extended mnemonic mfummcr2Alan Modra1-0/+5
2021-03-31Use bool in opcodesAlan Modra1-0/+18
2021-03-31Remove bfd_stdint.hAlan Modra1-0/+14
2021-03-30x86: drop seg_entryJan Beulich1-0/+7
2021-03-30x86: drop REGNAM_{AL,AX,EAX}Jan Beulich1-0/+4
2021-03-30x86: adjust st(<N>) parsingJan Beulich1-0/+7
2021-03-29x86: move some opcode table entriesJan Beulich1-0/+10
2021-03-29x86: VPSADBW's source operands are also commutativeJan Beulich1-0/+6
2021-03-29x86: fold SSE2AVX and their base MMX/SSE templatesJan Beulich1-0/+7
2021-03-29x86: undo Prefix_0X<nn> use in opcode tableJan Beulich1-0/+8
2021-03-29x86: shrink some struct insn_template fieldsJan Beulich1-0/+6
2021-03-29x86: derive opcode encoding space attribute from base opcodeJan Beulich1-0/+10
2021-03-29TRUE/FALSE simplificationAlan Modra1-0/+21
2021-03-29opcodes int vs bfd_boolean fixesAlan Modra1-0/+5