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2020-07-14x86-64: Zero-extend lower 32 bits displacement to 64 bitsH.J. Lu1-0/+6
Since the addr32 (0x67) prefix zero-extends the lower 32 bits address to 64 bits, change disassembler to zero-extend the lower 32 bits displacement to 64 bits when there is no base nor index registers. gas/ PR gas/26237 * testsuite/gas/i386/addr32.s: Add tests for 32-bit wrapped around address. * testsuite/gas/i386/x86-64-addr32.s: Likewise. * testsuite/gas/i386/addr32.d: Updated. * testsuite/gas/i386/x86-64-addr32-intel.d: Likewise. * testsuite/gas/i386/x86-64-addr32.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-addr32-intel.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-addr32.d: Likewise. opcodes/ PR gas/26237 * i386-dis.c (OP_E_memory): Without base nor index registers, 32-bit displacement to 64 bits.
2020-07-14arc: Detect usage of illegal double register pairsClaudiu Zissulescu1-0/+5
ARC can use odd-even double register pairs in some selected instructions. Although the GNU assembler doesn't allow even-odd registers to be used, there may be cases when the disassembler is presented with such situation. This patch add a test and detects such cases. opcodes/ 2020-07-14 Claudiu Zissulescu <claziss@gmail.com> * arc-dis.c (print_insn_arc): Detect and emit a warning when a faulty double register pair is detected. binutils/ 2020-07-14 Claudiu Zissulescu <claziss@gmail.com> * testsuite/binutils-all/arc/double_regs.s: New test. * testsuite/binutils-all/arc/objdump.exp: Add the above test. Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
2020-07-14x86/Intel: debug registers are named DRnJan Beulich1-0/+4
%db<n> is an AT&T invention; the Intel documentation and MASM have only ever specified DRn (in line with CRn and TRn). (In principle gas also shouldn't accept the names in Intel mode, but at least for now I've kept things as they are. Perhaps as a first step this should just be warned about.)
2020-07-14x86: drop Rm and the 'L' macroJan Beulich1-0/+13
Rm (and hence OP_R()) can be dropped by making 'Z' force modrm.mod to 3 (for OP_E()) instead of ignoring it. While at it move 'Z' handling to its designated place (after 'Y'; 'W' handling will be moved by a later change). Moves to/from TRn are illegal in 64-bit mode and thus get converted to honor this at the same time (also getting them in line with moves to/from CRn/DRn ModRM.mod handling wise). This then also frees up the L macro.
2020-07-14x86: drop Rdq, Rd, and MaskRJan Beulich1-0/+20
Rdq, Rd, and MaskR can be replaced by Edq, Ed / Rm, and MaskE respectively, as OP_R() doesn't enforce ModRM.mod == 3, and hence where MOD matters but hasn't been decoded yet it needs to be anyway. (The case of converting to Rm is temporary until a subsequent change.)
2020-07-14x86: simplify decode of opcodes valid only without any (embedded) prefixJan Beulich1-0/+19
In this case there's no need to go through prefix_table[] at all - the .prefix_requirement == PREFIX_OPCODE machinery takes care of this case already. A couple of further adjustments are needed though: - Gv / Ev and alike then can't be used (needs to be Gdq / Edq instead), - dq_mode and friends shouldn't lead to PREFIX_DATA getting set in used_prefixes.
2020-07-14x86: also use %BW / %DQ for kshift*Jan Beulich1-0/+18
2020-07-14x86: simplify decode of opcodes valid with (embedded) 66 prefix onlyJan Beulich1-0/+338
The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].
2020-07-14x86: drop further EVEX table entries that can be served by VEX onesJan Beulich1-0/+13
A few cases were missed by 6df22cf64c93 ("x86: drop EVEX table entries that can be served by VEX ones").
2020-07-14x86: drop need_vex_regJan Beulich1-0/+21
It was quite odd for the prior operand handling to have to clear this flag for the actual operand handling to print nothing. Have the actual operand handling determine whether the operand is actually present. With this {d,q}_scalar_swap_mode become unused and hence also get dropped.
2020-07-14x86: drop Vex128 and Vex256Jan Beulich1-0/+17
These are only used when VEX.L or EVEX.L'L have already been decoded, and hence the "normal" length dependent name determination is quite fine. Adjust a few enumerators to make clear that vex_len_table[] has been consulted; be consistent and do so for all *f128 and *i128 insns in one go.
2020-07-14x86: replace %LW by %DQJan Beulich1-0/+7
This makes more visible what the two alternatives will be that result from this macro.
2020-07-14x86: merge/move logic determining the EVEX disp8 shiftJan Beulich1-0/+7
Fold redundant case blocks and move the extra adjustments logic into the single case block that actually needs it - there's no need to go through the extra logic for all the other cases. Also utilize there that vex.b cannot be set at this point, due to earlier logic. Reduce the comment there, which was partly stale anyway.
2020-07-14x86: extend %BW use to VP{COMPRESS,EXPAND}{B,W}Jan Beulich1-0/+13
Unlike the earlier ones these also need their operands adjusted. Replace the (mis-described: there's nothing "scalar" here) {b,w}_scalar_mode by a single new mode, with the actual unit width controlled by EVEX.W.
2020-07-14x86-64: fix {,V}PCMPESTR{I,M} disassembly in Intel modeJan Beulich1-0/+14
The operands don't allow disambiguating the insn in 64-bit mode, and hence suffixes need to be emitted not just in AT&T mode. Achieve this by re-using %LQ while dropping PCMPESTR_Fixup().
2020-07-14x86: fold VCMP_Fixup() into CMP_Fixup()Jan Beulich1-0/+9
There's no reason to have two functions and two tables, when the AVX functionality here is a proper superset of the SSE one.
2020-07-14x86: don't disassemble MOVBE with two suffixesJan Beulich1-0/+6
MOVBE_Fixup() is entirely redundant with the S macro already used on the mnemonics, leading to double suffixes in suffix-always mode. Drop the function.
2020-07-14x86: avoid attaching suffix to register-only CRC32Jan Beulich1-0/+5
Just like other insns with GPR operands, CRC32 with only register operands should not get a suffix added unless in suffix-always mode. Do away with CRC32_Fixup() altogether, using other more generic logic instead.
2020-07-14x86-64: don't hide an empty but meaningless REX prefixJan Beulich1-0/+5
Unlike for non-zero values passed to USED_REX(), where rex_used gets updated only when the respective bit was actually set in the encoding, zero getting passed in is not further guarded, yet such a (potentially "empty") REX prefix takes effect only when there are registers numbered 4 and up.
2020-07-14x86: drop dead code from OP_IMREG()Jan Beulich1-0/+8
There's only a very limited set of modes that this function gets invoked with - avoid it being more generic than it needs to be. This may, down the road, allow actually doing away with the function altogether. This eliminates a first improperly used "USED_REX (0)".
2020-07-10x86: Add support for Intel AMX instructionsLili Cui1-0/+78
gas/ * doc/c-i386.texi: Document amx_int8, amx_bf16 and amx_tile. * config/tc-i386.c (i386_error): Add invalid_sib_address. (cpu_arch): Add .amx_int8, .amx_bf16 and .amx_tile. (cpu_noarch): Add noamx_int8, noamx_bf16 and noamx_tile. (match_simd_size): Add tmmword check. (operand_type_match): Add tmmword. (type_names): Add rTMM. (i386_error): Add invalid_tmm_register_set. (check_VecOperands): Handle invalid_sib_address and invalid_tmm_register_set. (match_template): Handle invalid_sib_address. (build_modrm_byte): Handle non-vector SIB and zmmword. (i386_index_check): Disallow RegIP for non-vector SIB. (check_register): Handle zmmword. * testsuite/gas/i386/i386.exp: Add AMX new tests. * testsuite/gas/i386/intel-regs.d: Add tmm. * testsuite/gas/i386/intel-regs.s: Add tmm. * testsuite/gas/i386/x86-64-amx-intel.d: New. * testsuite/gas/i386/x86-64-amx-inval.l: New. * testsuite/gas/i386/x86-64-amx-inval.s: New. * testsuite/gas/i386/x86-64-amx.d: New. * testsuite/gas/i386/x86-64-amx.s: New. * testsuite/gas/i386/x86-64-amx-bad.d: New. * testsuite/gas/i386/x86-64-amx-bad.s: New. opcodes/ * i386-dis.c (TMM): New. (EXtmm): Likewise. (VexTmm): Likewise. (MVexSIBMEM): Likewise. (tmm_mode): Likewise. (vex_sibmem_mode): Likewise. (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise. (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise. (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise. (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise. (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise. (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise. (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise. (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise. (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise. (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise. (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise. (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise. (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise. (PREFIX_VEX_0F3849_X86_64): Likewise. (PREFIX_VEX_0F384B_X86_64): Likewise. (PREFIX_VEX_0F385C_X86_64): Likewise. (PREFIX_VEX_0F385E_X86_64): Likewise. (X86_64_VEX_0F3849): Likewise. (X86_64_VEX_0F384B): Likewise. (X86_64_VEX_0F385C): Likewise. (X86_64_VEX_0F385E): Likewise. (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise. (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise. (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise. (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise. (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise. (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise. (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise. (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise. (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise. (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise. (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise. (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise. (VEX_W_0F3849_X86_64_P_0): Likewise. (VEX_W_0F3849_X86_64_P_2): Likewise. (VEX_W_0F3849_X86_64_P_3): Likewise. (VEX_W_0F384B_X86_64_P_1): Likewise. (VEX_W_0F384B_X86_64_P_2): Likewise. (VEX_W_0F384B_X86_64_P_3): Likewise. (VEX_W_0F385C_X86_64_P_1): Likewise. (VEX_W_0F385E_X86_64_P_0): Likewise. (VEX_W_0F385E_X86_64_P_1): Likewise. (VEX_W_0F385E_X86_64_P_2): Likewise. (VEX_W_0F385E_X86_64_P_3): Likewise. (names_tmm): Likewise. (att_names_tmm): Likewise. (intel_operand_size): Handle void_mode. (OP_XMM): Handle tmm_mode. (OP_EX): Likewise. (OP_VEX): Likewise. * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE. (operand_type_shorthands): Add RegTMM. (operand_type_init): Likewise. (operand_types): Add Tmmword. (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE. (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE. * i386-opc.h (CpuAMX_INT8): New. (CpuAMX_BF16): Likewise. (CpuAMX_TILE): Likewise. (SIBMEM): Likewise. (Tmmword): Likewise. (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile. (i386_opcode_modifier): Extend width of fields vexvvvv and sib. (i386_operand_type): Add tmmword. * i386-opc.tbl: Add AMX instructions. * i386-reg.tbl: Add AMX registers. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2020-07-08x86: various XOP insns lack L and/or W bit decodingJan Beulich1-0/+57
While some insns support both XOP.W based operand swapping and 256-bit operation (XOP.L=1), many others don't support one or both. For {L,S}LWPCB also fix the so far not decoded ModRM.mod == 3 restriction. Take the opportunity and replace the custom OP_LWP_E() and OP_LWPCB_E() routines by suitable other, non-custom operanbd specifiers.
2020-07-08x86: FMA4 scalar insns ignore VEX.LJan Beulich1-0/+12
Just like other VEX-encoded scalar insns do. Besides a testcase for this behavior also introduce one to verify that XOP scalar insns don't honor -mavxscalar=256, as they don't ignore XOP.L.
2020-07-08x86: re-work operand swapping for XOP shift/rotate insnsJan Beulich1-0/+8
There's no need for custom operand handling here, except for the VEX.W controlled operand swapping.
2020-07-08x86: re-work operand handling for 5-operand XOP insnsJan Beulich1-0/+10
There's no need for custom operand handling here, except for the VEX.W controlled operand swapping and the printing of the remaining 4-bit immediate. VEX.W can be handled just like 4-operand insns. Also take the opportunity and drop the stray indirection through vex_w_table[].
2020-07-08x86: re-work operand swapping for FMA4 and 4-operand XOP insnsJan Beulich1-0/+7
There's no need for custom operand handling here, except for the VEX.W controlled operand swapping. The latter can be easily integrated into OP_REG_VexI4().
2020-07-07arc: Update vector instructions.Claudiu Zissulescu1-0/+8
Update vadd2, vadd4h, vmac2h, vmpy2h, vsub4h vector instructions arguments to discriminate between double/single register operands. opcodes/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * arc-opc.c (insert_rbd): New function. (RBD): Define. (RBDdup): Likewise. * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update instructions. Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
2020-07-07x86: introduce %BW to avoid going through vex_w_table[]Jan Beulich1-0/+13
This parallels %LW and %XW.
2020-07-06x86: adjust/correct VFRCZ{P,S}{S,D} decodingJan Beulich1-0/+12
The unnecessary XOP.L decoding had caught my eye, together with the not really expected operand specifiers. Drop this decode step, and instead make sure XOP.W and XOP.PP don't get ignored. For the latter, do this in a form applicable to all XOP insns, rather than adding extra table layers - there are no encodings with the field non-zero. Besides these two, for the scalar forms XOP.L actually needs to also be zero.
2020-07-06x86: use %LW / %XW instead of going through vex_w_table[]Jan Beulich1-0/+14
Since we have these macros, there's no point having unnecessary table depth. VFPCLASSP{S,D} are now the first instance of using two %-prefixed macros, which has pointed out a problem with the implementation. Instead of using custom code in various case blocks, do the macro accumulation centralized at the top of the main loop of putop(), and zap the accumulated macros at the bottom of that loop once it has been processed.
2020-07-06x86: most VBROADCAST{F,I}{32,64}x* only accept memory operandsJan Beulich1-0/+26
VBROADCAST{F,I}32x2 are the only exceptions here.
2020-07-06x86: adjust/correct V*{F,I}{32x8,64x4}Jan Beulich1-0/+8
For all of these only the 512-bit forms are valid, so drop 256-bit ones from the integer insert/extract variants. Also replace EXxmmq by the more natural (here) EXymm.
2020-07-06x86: drop EVEX table entries that can be made served by VEX onesJan Beulich1-0/+32
By doing the EVEX.W decode first, in various cases VEX table entries can be re-used.
2020-07-06x86: AVX512 VPERM{D,Q,PS,PD} insns need to honor EVEX.L'LJan Beulich1-0/+11
Just like (where they exist) their AVX counterparts do for VEX.L. For all of them the 128-bit forms are invalid.
2020-07-06x86: AVX512 extract/insert insns need to honor EVEX.L'LJan Beulich1-0/+13
Just like their AVX counterparts do for VEX.L. At this occasion also make EVEX.W have the same effect as VEX.W on the printing of VPINSR{B,W}'s operands, bringing them also in sync with VPEXTR{B,W}.
2020-07-06x86: honor VEX.W for VCVT{PH2PS,PS2PH}Jan Beulich1-0/+14
Unlike for the EVEX-encoded versions, the VEX ones failed to decode VEX.W. Once the necessary adjustments are done, it becomes obvious that the EVEX and VEX table entries for VCVTPS2PH are identical and can hence be folded.
2020-07-06x86: drop EVEX table entries that can be served by VEX onesJan Beulich1-0/+78
The duplication is not only space inefficient, but also risks entries going out of sync (some of which that I became aware of while doing this work will get addressed subsequently). Right here note that for VGF2P8MULB this also addresses the prior lack of EVEX.W decoding (i.e. a first example of out of sync entries). This introduces EXxEVexR to some VEX templates, on the basis that this operand is benign there and only relevant when EVEX encoding ends up reaching these entries.
2020-07-06x86: replace EXqScalarS by EXqVexScalarSJan Beulich1-0/+6
There's only a single user, that that one can do fine with the alternative, as the "Vex" aspect of the other operand kind is meaningful only on 3-operand insns. While doing this I noticed that I didn't need to do the same adjustment in the EVEX tables, and voilà - there was a bug, which gets fixed at the same time (see the testsuite changes).
2020-07-06x86: replace EX{d,q}Scalar by EXxmm_m{d,q}Jan Beulich1-0/+12
Along the lines of 4102be5cf925 ("x86: replace EXxmm_mdq by EXVexWdqScalar"), but in the opposite direction, replace EXdScalar/ EXqScalar by EXxmm_md/EXxmm_mq respectively, rendering d_scalar_mode and q_scalar_mode unused. The change is done this way to improve telling apart operands affected here from ones using EXbScalar/EXwScalar, which work sufficiently differently. Additionally this increases similarity between several VEX-encoded insns and their EVEX-encoded counterparts.
2020-07-06Fix spelling mistakes in some of the binutils sub-directories.Nick Clifton1-0/+6
PR 26204 gas * config/tc-arm.c: Fix spelling mistake. * config/tc-riscv.c: Likewise. * config/tc-z80.c: Likewise. * po/gas.pot: Regenerate. ld * lexsup.c: Fix spelling mistake. * po/ld.pot: Regenerate. opcodes * arc-dis.c: Fix spelling mistake. * po/opcodes.pot: Regenerate.
2020-07-06Updated translations for various binutils sub-directoriesNick Clifton1-0/+5
2020-07-04Update version to 2.35.50 and regenerate filesNick Clifton1-0/+5
2020-07-04Add markers for binutils 2.35 branchNick Clifton1-0/+4
2020-07-02x86: Add SwapSourcesH.J. Lu1-0/+9
We check register-only source operand to decide if two source operands of VEX encoded instructions should be swapped. But source operands in AMX instructions with two source operands swapped are all register-only operand. Add SwapSources to indicate two source operands should be swapped. gas/ * config/tc-i386.c (build_modrm_byte): Check vexswapsources to swap two source operands. opcodes/ * i386-gen.c (opcode_modifiers): Add VexSwapSources. * i386-opc.h (VexSwapSources): New. (i386_opcode_modifier): Add vexswapsources. * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions with two source operands swapped. * i386-tbl.h: Regenerated.
2020-06-30RISC-V: Support debug and float CSR as the unprivileged ones.Nelson Chu1-0/+5
The unprivileged CSR should be controlled by other specific specs rather than the privileged spec. For example, the debug CSR should be controlled by the debug spec, and the float CSR should be controlled by the float spec. User may use assembler options to choose what the debug and other specs they want, or may encode the versions of specs into the architecture string directly. Since we haven't decided which one is better, we set the defined and aborted versions of unprivileged CSR to PRIV_SPEC_CLASS_NONE in the include/opcode/riscv-opc.h, to tell assembler don't check priv spec versions for them. However, these PRIV_SPEC_CLASS_NONE will be changed to FLOAT_SPEC_CLASS_* and DEBUG_SPEC_CLASS_* in the future. gas/ * config/tc-riscv.c (riscv_csr_class_check): Removed. Move the checking into riscv_csr_address. (riscv_csr_version_check): Likewise. (riscv_csr_address): New function. Return the suitable CSR address after checking the ISA dependency and versions. Issue warnings if we find any conflict and -mcsr-check is set. CSR_CLASS_F and CSR_CLASS_DEBUG are unprivileged CSR for now, so don't check the priv spec versions for them. (reg_csr_lookup_internal): Call riscv_csr_address to find the suitable CSR address. * testsuite/gas/riscv/priv-reg-fail-fext.d: Remove -mpriv-spec=1.11. * testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise. * testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise. * testsuite/gas/riscv/priv-reg-fail-fext.l: We don't care the priv spec warnings here. These warnings are added by accident. Remove them and only focus on the ISA dependency warnings. * testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Updated since dscratch0 and dscratch1 are regarded as the unprivileged CSR rather than the privileged ones. * testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise. * testsuite/gas/riscv/priv-reg.s: Likewise. Add missing debug CSR. * testsuite/gas/riscv/priv-reg-version-1p9.d: Likewise. * testsuite/gas/riscv/priv-reg-version-1p9p1.d: Likewise. * testsuite/gas/riscv/priv-reg-version-1p10.d: Likewise. * testsuite/gas/riscv/priv-reg-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-dw-regnums.d: Likewise. * testsuite/gas/riscv/csr-dw-regnums.s: Likewise. include/ * opcode/riscv-opc.h: Support the unprivileged CSR. The versions of the unprivileged CSR should be PRIV_SPEC_CLASS_NONE for now. * opcode/riscv.h (enum riscv_csr_class): Add CSR_CLASS_DEBUG. opcodes/ * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the unprivileged CSR can also be initialized.
2020-06-29C++ commentsAlan Modra1-0/+10
binutils isn't c99 (yet). This replaces or removes some C++ style comments. bfd/ * arc-got.h: Use C style comments. * coff-z80.c: Likewise. * elf32-csky.c: Likewise. * peXXigen.c: Likewise. * elf32-m32c.c (m32c_elf_relax_delete_bytes): Remove commented out code. binutils/ * dwarf.c: Use C style comments. * resrc.c: Likewise. gas/ * config/tc-s12z.c: Use C style comments. * config/tc-z80.c: Likewise. * config/tc-xtensa.c (emit_ld_r_n): Remove commented out code. include/ * coff/internal.h: Use C style comments. * coff/pe.h: Likewise. * elf/ppc64.h: Likewise. opcodes/ * arm-dis.c: Use C style comments. * cr16-opc.c: Likewise. * ft32-dis.c: Likewise. * moxie-opc.c: Likewise. * tic54x-dis.c: Likewise. * s12z-opc.c: Remove useless comment. * xgate-dis.c: Likewise.
2020-06-26i386-opc.tbl: Add a blank lineH.J. Lu1-0/+4
* i386-opc.tbl: Add a blank line.
2020-06-26x86: Correct VexSIB128 to VecSIB128H.J. Lu1-2/+2
2020-06-26x86: Rename VecSIB to SIB for Intel AMXH.J. Lu1-0/+18
Rename VecSIB to SIB to support Intel Advanced Matrix Extensions which introduces instructions with a mandatory SIB byte which isn't a vector SIB (VSIB). gas/ * config/tc-i386.c (check_VecOperands): Replace vecsib with sib. Replace VecSIB128, VecSIB256 and VecSIB512 with VECSIB128, VECSIB256 and VECSIB512, respectively. (build_modrm_byte): Replace vecsib with sib. opcodes/ * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB. (VecSIB128): Renamed to ... (VECSIB128): This. (VecSIB256): Renamed to ... (VECSIB256): This. (VecSIB512): Renamed to ... (VECSIB512): This. (VecSIB): Renamed to ... (SIB): This. (i386_opcode_modifier): Replace vecsib with sib. * i386-opc.tbl (VexSIB128): New. (VecSIB256): Likewise. (VecSIB512): Likewise. Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VexSIB128, VecSIB256 and VecSIB512, respectively.
2020-06-26x86: make I disassembler macro available for new useJan Beulich1-0/+7
The {Q|Q} construct on lgdt/lidt and the slightly different {Q|IQ} struck me as odd when encountering. Realizing they both have the same effect, let's free up the I macro by using the former form of construct where needed (there aren't that many uses overall). With there now being several multi-character macros also re-do "alt" handling slightly: Terminate it when finding the closing brace, rather than after the next single character. Also set the flag only when actually in Intel syntax mode.
generated by cgit v1.1 at 2025-02-20 06:02:23 +0000