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2015-12-04Fix failures in the GAS testsuite for the ARC architecture.Claudiu Zissulescu1-0/+8
2015-12-02Fix ldah being disassembled as ldaexhAndre Vieira1-0/+5
2015-11-27[AArch64][PATCH 3/3] Add floating-point FP16 instructionsMatthew Wahab1-0/+18
2015-11-27[AArch64][PATCH 2/3] Adjust a utility function for floating point values.Matthew Wahab1-0/+10
2015-11-27[AArch64][PATCH 1/3] Support ARMv8.2 FP16 floating point instructions.Matthew Wahab1-0/+5
2015-11-27[AArch64] Add ARMv8.2 instruction alias REV64.Matthew Wahab1-0/+8
2015-11-27[AArch64] Add ARMv8.2 instructions BFC and REV64.Matthew Wahab1-0/+16
2015-11-27[AArch64] Let aliased instructions be their preferred form.Matthew Wahab1-0/+8
2015-11-27[Aarch64] Support an ARMv8.2 system register.Matthew Wahab1-0/+6
2015-11-23opcodes: handle mach-o for thumb/arm disambiguation.Tristan Gingold1-0/+4
2015-11-20[AArch64] Add support for ARMv8.1 Virtulization Host Extensions.Matthew Wahab1-0/+12
2015-11-20Remove a if-clause that is redundant because the same test has been performed...Nick Clifton1-0/+5
2015-11-20Update translations.Nick Clifton1-0/+4
2015-11-19[AArch64] Reject invalid immediate operands to MSR PANMatthew Wahab1-0/+5
2015-11-17Fix the disassembly of conditional instructions will illegal condition select...Nick Clifton1-0/+5
2015-11-14Bump version to 2.26.51Tristan Gingold1-0/+4
2015-11-11Add assembler, disassembler and linker support for power9.Peter Bergner1-0/+51
2015-11-02Disassemble RX NOP instructions as such.Nick Clifton1-0/+6
2015-11-02Fix disassembly of RX zero-offset register indirect instructions.Nick Clifton1-0/+7
2015-10-28Pass noaliases_p to aarch64_decode_insnYao Qi1-0/+8
2015-10-27Fix RL78 disassembly of DE+offset addressing to always show the offset, even ...Vinay Kumar1-0/+7
2015-10-27Display system registers by their names when disassembling RL78 instructions.Vinay Kumar1-0/+9
2015-10-27Fix RL78 disassembly so that SP+OFFSET addressing always shows the offset, ev...Vinay Kumar1-0/+7
2015-10-14Add missing changelog entriesAndreas Krebbel1-0/+7
2015-10-08Fix compile time warning compiling ARC port.Nick Clifton1-0/+4
2015-10-07Avoid using 'template' C++ keywordYao Qi1-0/+6
2015-10-07New ARC implementation.Nick Clifton1-0/+11
2015-10-02[aarch64] expose disas_aarch64_insn and rename it to aarch64_decode_insnYao Qi1-0/+7
2015-10-02[aarch64] Remove argument pc from disas_aarch64_insnYao Qi1-0/+5
2015-09-29Add support for extensions in the .machine pseudoop on S/390, e.g. ".machine ...Dominik Vogt1-0/+6
2015-09-28Updare French translation for binutils and German translation for opcodes.Nick Clifton1-0/+4
2015-09-28Patches for illegal ppc 500 instructionsTom Rix1-0/+4
2015-09-23Fix compile time warnings generated when compiling with clang.Nick Clifton1-0/+18
2015-09-22Enhance the RX disassembler to detect and report bad instructions.Nick Clifton1-0/+12
2015-09-22opcodes/ppc-opc.c: Add dscr and ctrl SPR mnemonicsAnton Blanchard1-0/+4
2015-08-25Support for the sparc %pmcdper privileged register.Jose E. Marchesi1-0/+5
2015-08-24Fix the partial disassembly of a broken three byte instruction at the end of ...Jan Stancek1-0/+4
2015-08-21PR binutils/18257: Properly decode x86/Intel mask instructions.Alexander Fomin1-0/+37
2015-08-17Trailing space in opcodes/ generated filesAlan Modra1-0/+9
2015-08-13Fixes for unpredictable nops and 26-bit versions of teq,tst,cmn,cmp.Andre Vieira1-0/+8
2015-08-12[MIPS] Map 'move' to 'or'.Simon Dardis1-0/+6
2015-08-11Fix the disassembly of the AArch64 SIMD EXT instruction.Nick Clifton1-0/+6
2015-08-10Add SIGRIE instruction for MIPS R6Robert Suchanek1-0/+4
2015-08-07Remove CpuFMA4 support from CPU_ZNVER1_FLAGS.Amit Pawar1-0/+5
2015-07-30Properly disassemble movnti in Intel modeH.J. Lu1-0/+10
2015-07-27Regenerate configure filesH.J. Lu1-0/+4
2015-07-23Fix ubsan signed integer overflowAlan Modra1-1/+6
2015-07-22Fix memory operand size for vcvtt?ps2u?qq instructionsH.J. Lu1-0/+9
2015-07-16Updates the ARM disassembler's output of floating point constants to include ...Alessandro Marzocchi1-0/+7
2015-07-14Sync config/warnings.m4 with GCCH.J. Lu1-0/+4
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