| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2018-01-08 | x86: Properly encode vmovd with 64-bit memeory | H.J. Lu | 1 | -0/+7 |
| 2018-01-05 | RISC-V: Print symbol address for jalr w/ zero offset. | Jim Wilson | 1 | -0/+5 |
| 2018-01-03 | Update year range in copyright notice of binutils files | Alan Modra | 1 | -0/+4 |
| 2018-01-03 | ChangeLog rotation | Alan Modra | 1 | -1965/+2 |
| 2018-01-02 | x86: partial revert of 10c17abdd0 | Jan Beulich | 1 | -0/+5 |
| 2017-12-20 | RISC-V: Add compressed instruction hints, and a few misc cleanups. | Jim Wilson | 1 | -0/+11 |
| 2017-12-19 | Correct disassembly of dot product instructions. | Tamar Christina | 1 | -0/+10 |
| 2017-12-19 | Add support for V_4B so we can properly reject it. | Tamar Christina | 1 | -0/+5 |
| 2017-12-18 | x86: fold certain AVX and AVX2 templates | Jan Beulich | 1 | -0/+38 |
| 2017-12-18 | x86: fold RegXMM/RegYMM/RegZMM into RegSIMD | Jan Beulich | 1 | -0/+18 |
| 2017-12-18 | x86: drop FloatReg and FloatAcc | Jan Beulich | 1 | -0/+10 |
| 2017-12-18 | x86: replace Reg8, Reg16, Reg32, and Reg64 | Jan Beulich | 1 | -0/+20 |
| 2017-12-15 | Fix disassembly for PowerPC | Dimitar Dimitrov | 1 | -0/+5 |
| 2017-12-15 | x86: drop stray CheckRegSize uses | Jan Beulich | 1 | -0/+9 |
| 2017-12-13 | Add missing RISC-V fsrmi and fsflagsi instructions. | Jim Wilson | 1 | -0/+5 |
| 2017-12-13 | This patch enables disassembler_needs_relocs for PRU. It is needed to print c... | Dimitar Dimitrov | 1 | -0/+4 |
| 2017-12-11 | [Binutils][Objdump]Check symbol section information while search a mapping sy... | Renlin Li | 1 | -0/+6 |
| 2017-12-03 | Fix "FAIL: VLE relocations 3" | Alan Modra | 1 | -0/+4 |
| 2017-12-01 | Use consistent types for holding instructions, instruction masks, etc. | Peter Bergner | 1 | -0/+51 |
| 2017-11-30 | x86: derive DispN from BaseIndex | Jan Beulich | 1 | -0/+17 |
| 2017-11-30 | x86: drop Vec_Disp8 | Jan Beulich | 1 | -0/+10 |
| 2017-11-29 | Support --localedir, --datarootdir and --datadir | Stefan Stroe | 1 | -0/+6 |
| 2017-11-27 | Update the simplified Chinese translation of the messages in the opcodes libr... | Nick Clifton | 1 | -0/+4 |
| 2017-11-24 | x86: don't omit disambiguating suffixes from "fi*" | Jan Beulich | 1 | -0/+5 |
| 2017-11-23 | Add Disp8MemShift for AVX512 VAES instructions. | Igor Tsimbalist | 1 | -0/+5 |
| 2017-11-23 | x86: fix AVX-512 16-bit addressing | Jan Beulich | 1 | -0/+5 |
| 2017-11-23 | x86: correct UDn | Jan Beulich | 1 | -0/+8 |
| 2017-11-22 | Remove Vec_Disp8 field for vgf2p8mulb for AVX flavor. | Igor Tsimbalist | 1 | -0/+5 |
| 2017-11-22 | Update ChangeLog | Igor Tsimbalist | 1 | -0/+5 |
| 2017-11-22 | [ARC] Fix handling of ARCv2 H-register class. | claziss | 1 | -0/+4 |
| 2017-11-21 | [ARC] Improve printing of pc-relative instructions. | claziss | 1 | -0/+5 |
| 2017-11-16 | Add new AArch64 FP16 FM{A|S} instructions. | Tamar Christina | 1 | -0/+5 |
| 2017-11-16 | Add assembler and disassembler support for the new Armv8.4-a instructions for... | Tamar Christina | 1 | -0/+10 |
| 2017-11-16 | x86: ignore high register select bit(s) in 32- and 16-bit modes | Jan Beulich | 1 | -0/+11 |
| 2017-11-15 | x86: use correct register names | Jan Beulich | 1 | -0/+5 |
| 2017-11-15 | x86: drop VEXI4_Fixup() | Jan Beulich | 1 | -0/+8 |
| 2017-11-15 | x86-64: don't allow use of %axl as accumulator | Jan Beulich | 1 | -0/+5 |
| 2017-11-14 | x86: add disassembler support for XOP VPCOM* pseudo-ops | Jan Beulich | 1 | -0/+5 |
| 2017-11-14 | x86: add support for AVX-512 VPCMP*{B,W} pseudo-ops | Jan Beulich | 1 | -0/+13 |
| 2017-11-14 | x86: string insns don't allow displacements | Jan Beulich | 1 | -0/+6 |
| 2017-11-13 | x86: {f,}xsave64 / {f,}xrstor64 / xsaveopt64 should not allow q suffix | Jan Beulich | 1 | -0/+6 |
| 2017-11-09 | Add assembler and disassembler support for the new Armv8.4-a registers for AA... | Tamar Christina | 1 | -0/+17 |
| 2017-11-09 | Add the operand encoding types for the new Armv8.2-a back-ported instructions... | Tamar Christina | 1 | -0/+7 |
| 2017-11-09 | Adds the new Fields and Operand types for the new instructions in Armv8.4-a. | Tamar Christina | 1 | -0/+21 |
| 2017-11-09 | Split the ARM Crypto ISA extensions for AES and SHA1+2 into their own options... | Tamar Christina | 1 | -0/+10 |
| 2017-11-08 | Split the AArch64 Crypto instructions for AES and SHA1+2 into their own optio... | Nick Clifton | 1 | -0/+11 |
| 2017-11-08 | Adds command line support for Armv8.4-A, via the new command line option -mar... | Jiong Wang | 1 | -0/+6 |
| 2017-11-07 | opcodes/arc: Fix incorrect insn_class for some nps insns | Andrew Burgess | 1 | -0/+4 |
| 2017-11-07 | ngettext support | Alan Modra | 1 | -0/+8 |
| 2017-11-03 | [ARC] Force the disassam to use the hexadecimal number for printing | claziss | 1 | -0/+8 |
