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AgeCommit message (Expand)AuthorFilesLines
2015-08-11Fix the disassembly of the AArch64 SIMD EXT instruction.Nick Clifton1-0/+6
2015-08-10Add SIGRIE instruction for MIPS R6Robert Suchanek1-0/+4
2015-08-07Remove CpuFMA4 support from CPU_ZNVER1_FLAGS.Amit Pawar1-0/+5
2015-07-30Properly disassemble movnti in Intel modeH.J. Lu1-0/+10
2015-07-27Regenerate configure filesH.J. Lu1-0/+4
2015-07-23Fix ubsan signed integer overflowAlan Modra1-1/+6
2015-07-22Fix memory operand size for vcvtt?ps2u?qq instructionsH.J. Lu1-0/+9
2015-07-16Updates the ARM disassembler's output of floating point constants to include ...Alessandro Marzocchi1-0/+7
2015-07-14Sync config/warnings.m4 with GCCH.J. Lu1-0/+4
2015-07-10Add missing changelog entriesAlan Modra1-0/+4
2015-07-03Remove ppc860, ppc750cl, ppc7450 insns from common ppc.Alan Modra1-0/+6
2015-07-01Opcodes and assembler support for Nios II R2Sandra Loosemore1-0/+22
2015-06-30Add support for monitorx/mwaitx instructionsAmit Pawar1-0/+13
2015-06-22PPC sync instruction accepts invalid and incompatible operandsPeter Bergner1-0/+7
2015-06-22Stop "objdump -d" from disassembling past a symbolic address.Nick Clifton1-0/+14
2015-06-19Allow for optional operands with non-zero default values.Peter Bergner1-0/+11
2015-06-16[AArch64] Support id_mmfr4 system registerMatthew Wahab1-0/+4
2015-06-16Fixes a compile time warnng about left shifting a negative value.Szabolcs Nagy1-0/+4
2015-06-12Remove unused MTMSRD_L macro and re-add accidentally deleted comment.Peter Bergner1-0/+5
2015-06-04Fixes the check for emulated MSP430 instrucrtions that take no operands.Nick Clifton1-0/+5
2015-06-02[ARM] Add support for ARMv8.1 PAN extensionMatthew Wahab1-0/+5
2015-06-02[ARM] Rework CPU feature selection in the disassemblerMatthew Wahab1-0/+5
2015-06-02[AArch64] Support for ARMv8.1a Adv.SIMD instructionsMatthew Wahab1-0/+9
2015-06-02[AArch64] Support for ARMv8.1a Limited Ordering Regions extensionMatthew Wahab1-0/+10
2015-06-01[AArch64][libopcode] Add support for PAN architecture extensionMatthew Wahab1-0/+8
2015-06-01x86/Intel: fix i386_optab[] for vcvt{,u}si2s{d,s}Jan Beulich1-0/+4
2015-06-01x86/Intel: disassemble vcvt{,u}si2s{d,s} with correct operand orderJan Beulich1-0/+5
2015-06-01x86/Intel: accept mandated operand order for vcvt{,u}si2s{d,s}Jan Beulich1-0/+5
2015-05-18Remove Disp32 from AMD64 direct call/jmpH.J. Lu1-0/+5
2015-05-15Support AMD64/Intel ISAs in assembler/disassemblerH.J. Lu1-0/+20
2015-05-14Fix some PPC assembler errors.Peter Bergner1-0/+7
2015-05-13Add missing ChangeLog entries for PR binutis/18386H.J. Lu1-0/+13
2015-05-11Remove Disp16|Disp32 from 64-bit direct branchesH.J. Lu1-0/+7
2015-05-11Add Intel MCU support to opcodesH.J. Lu1-0/+13
2015-04-30Make RL78 disassembler and simulator respect ISA for mul/divDJ Delorie1-0/+15
2015-04-29Updated translations for various binutils components.Nick Clifton1-0/+4
2015-04-27opcodes/Peter Bergner1-0/+14
2015-04-27S/390: Fixes for z13 instructions.Andreas Krebbel1-0/+6
2015-04-23x86: disambiguate disassembly of certain AVX512 insnsJan Beulich1-0/+7
2015-04-15Remove the unused PREFIX_UD_XXXH.J. Lu1-0/+9
2015-04-15Check dp->prefix_requirement insteadH.J. Lu1-0/+6
2015-04-15Handle invalid prefixes for rdrand and rdseedH.J. Lu1-0/+14
2015-04-15Replace mandatory_prefix with prefix_requirementH.J. Lu1-0/+34
2015-04-15[ARM] Disassembles SSAT and SSAT16 instructions incorrectly for Thumb-2Renlin Li1-0/+6
2015-04-06x86: Use individual prefix control for each opcode.Ilya Tocar1-0/+29
2015-03-30opcodes: d10v: fix old style prototypeMike Frysinger1-0/+4
2015-03-29Add the missing opcodes/ChangeLog entryH.J. Lu1-0/+4
2015-03-26powerpc: Only initialise opcode indices onceAnton Blanchard1-0/+5
2015-03-26powerpc: Add slbfee. instructionAnton Blanchard1-0/+4
2015-03-24Extend arm_feature_set struct to provide more bitsTerry Guo1-0/+13
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