aboutsummaryrefslogtreecommitdiff
path: root/opcodes/ChangeLog
AgeCommit message (Expand)AuthorFilesLines
2015-04-30Make RL78 disassembler and simulator respect ISA for mul/divDJ Delorie1-0/+15
2015-04-29Updated translations for various binutils components.Nick Clifton1-0/+4
2015-04-27opcodes/Peter Bergner1-0/+14
2015-04-27S/390: Fixes for z13 instructions.Andreas Krebbel1-0/+6
2015-04-23x86: disambiguate disassembly of certain AVX512 insnsJan Beulich1-0/+7
2015-04-15Remove the unused PREFIX_UD_XXXH.J. Lu1-0/+9
2015-04-15Check dp->prefix_requirement insteadH.J. Lu1-0/+6
2015-04-15Handle invalid prefixes for rdrand and rdseedH.J. Lu1-0/+14
2015-04-15Replace mandatory_prefix with prefix_requirementH.J. Lu1-0/+34
2015-04-15[ARM] Disassembles SSAT and SSAT16 instructions incorrectly for Thumb-2Renlin Li1-0/+6
2015-04-06x86: Use individual prefix control for each opcode.Ilya Tocar1-0/+29
2015-03-30opcodes: d10v: fix old style prototypeMike Frysinger1-0/+4
2015-03-29Add the missing opcodes/ChangeLog entryH.J. Lu1-0/+4
2015-03-26powerpc: Only initialise opcode indices onceAnton Blanchard1-0/+5
2015-03-26powerpc: Add slbfee. instructionAnton Blanchard1-0/+4
2015-03-24Extend arm_feature_set struct to provide more bitsTerry Guo1-0/+13
2015-03-17Add znver1 processorGanesh Gopalasubramanian1-0/+11
2015-03-13MIPS: Fix constraint issues with the R6 beqc and bnec instructionsAndrew Bennett1-0/+5
2015-03-13Add support for MIPS R6 evp and dvp instructions.Andrew Bennett1-0/+4
2015-03-10S/390: Add more IBM z13 instructionsAndreas Krebbel1-0/+5
2015-03-10[AARCH64] Remove Load/Store register (unscaled immediate) alias.Jiong Wang1-0/+9
2015-03-03[ARM] Skip private symbol when doing objdumpJiong Wang1-0/+4
2015-02-25[SH] Fix clrs, sets, pref insn arch memberships.Oleg Endo1-0/+7
2015-02-23Adds a space between the operands of the RL78's MOV instruction for consisten...Vinay1-0/+6
2015-02-19Wrap a few opcodes headers in extern "C" for C++Pedro Alves1-0/+4
2015-02-10opcodes/microblaze: Rename 'or', 'and', 'xor' to avoid C++ conflictPedro Alves1-0/+7
2015-01-28FT32 initial supportAlan Modra1-0/+11
2015-01-28NDS32/opcodes: Add new system registers.Kuan-Lin Chen1-0/+4
2015-01-16S/390: Add support for IBM z13.Andreas Krebbel1-0/+18
2015-01-02ChangeLog rotatation and copyright year updateAlan Modra1-883/+4
2014-12-27Limit moxie sto/ldo offsets to 16 bitsAnthony Green1-0/+6
2014-12-24Add mul.x and umul.x instructions to moxie portAnthony Green1-0/+5
2014-12-16Add in a JALRC alias and fix the NAL instruction.Matthew Fortune1-0/+5
2014-12-12Add zex instructions for moxie portAnthony Green1-0/+4
2014-12-06Add Visium support to opcodesEric Botcazou1-0/+13
2014-11-30Power4 should treat mftb as extended mfspr mnemonicAlan Modra1-0/+5
2014-11-28Remove broken nios2 assembler dwim support.Sandra Loosemore1-0/+5
2014-11-28Don't deprecate powerpc mftb insnAlan Modra1-0/+6
2014-11-24Update libtool.m4 from GCC trunkH.J. Lu1-0/+4
2014-11-17Add AVX512VBMI instructionsIlya Tocar1-0/+14
2014-11-17Add AVX512IFMA instructionsIlya Tocar1-0/+13
2014-11-17Add pcommit instructionIlya Tocar1-0/+12
2014-11-17Add clwb instructionIlya Tocar1-0/+12
2014-11-06Add mach parameter to nios2_find_opcode_hash.Sandra Loosemore1-0/+5
2014-11-03Import updated translations supplied by the Translation Project.Nick Clifton1-0/+4
2014-10-31MIPS: Add Octeon 3 supportNaveen H.S1-0/+14
2014-10-29Updated/new translations provided by the Translations Project.Nick Clifton1-0/+4
2014-10-23Refactoring/cleanup of nios2 opcodes and assembler code.Sandra Loosemore1-0/+24
2014-10-21ppc: enable msgclr and msgsnd on Power8Jan Beulich1-0/+4
2014-10-17opcodes, elf: annotate instructions with HWCAP2_VIS3B.Jose E. Marchesi1-0/+1
generated by cgit v1.1 at 2024-12-16 09:12:21 +0000