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AgeCommit message (Expand)AuthorFilesLines
2015-12-15Add support for RX V2 Instruction SetYoshinori Sato1-0/+6
2015-12-14[AArch64][PATCH 14/14] Support FP16 Adv.SIMD Scalar Shift By Immediate instru...Matthew Wahab1-0/+9
2015-12-14[AArch64][PATCH 13/14] Support FP16 Adv.SIMD Shift By Immediate instructions.Matthew Wahab1-0/+9
2015-12-14[AArch64][PATCH 12/14] Support FP16 Adv.SIMD Scalar Pairwise instructions.Matthew Wahab1-0/+9
2015-12-14[AArch64][PATCH 11/14] Add support for the 2H vector type.Matthew Wahab1-0/+6
2015-12-14[AArch64][PATCH 9/14] Support FP16 Adv.SIMD Modified Immediate instructions.Matthew Wahab1-0/+9
2015-12-14[AArch64][PATCH 8/14] Support FP16 Adv.SIMD Across Lanes instructions.Matthew Wahab1-0/+9
2015-12-14[AArch64][PATCH 7/14] Support FP16 Scalar Indexed Element instructions.Matthew Wahab1-0/+8
2015-12-14[AArch64][PATCH 6/14] Support FP16 Vector Indexed Element instructions.Matthew Wahab1-0/+9
2015-12-14[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.Matthew Wahab1-0/+12
2015-12-14[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.Matthew Wahab1-0/+12
2015-12-14[AArch64][PATCH 3/14] Support ARMv8.2 FP16 Scalar Three Same instructions.Matthew Wahab1-0/+9
2015-12-14[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.Matthew Wahab1-0/+11
2015-12-14[AArch64][PATCH 1/14] Support ARMv8.2 FP16 Adv.SIMD instructions.Matthew Wahab1-0/+5
2015-12-14[AArch64] Fix errors rebasing the ARMv8.2 AT and system registers patchMatthew Wahab1-0/+8
2015-12-12Enable 2 operand form of powerpc mfcr with -manyAlan Modra1-0/+6
2015-12-11[AArch64][Patch 4/5] Support HINT aliases taking operands.Matthew Wahab1-0/+10
2015-12-11[AArch64][Patch 3/5] Adjust maximum number of instruction aliases.Matthew Wahab1-0/+4
2015-12-11[AArch64][Patch 2/5] Add Statistical Profiling Extension system registers.Matthew Wahab1-0/+9
2015-12-10[Aarch64] Support ARMv8.2 AT instructionsMatthew Wahab1-0/+6
2015-12-10[AArch64][PATCH 2/2] Support ARMv8.2 DC CVAP instruction.Matthew Wahab1-0/+5
2015-12-10[AArch64][PATCH 1/2] Add support for ARMv8.2 DC CVAP instruction.Matthew Wahab1-0/+13
2015-12-10[AArch64][binutils] Add support for ARMv8.2 PSTATE.UAO.Matthew Wahab1-0/+7
2015-12-10[AArch64][PATCH 2/2] Add RAS system registers.Matthew Wahab1-0/+8
2015-12-10[AArch64][PATCH 1/2] Add support for RAS instruction ESB.Matthew Wahab1-0/+8
2015-12-09Implement Intel OSPKE instructionsH.J. Lu1-0/+15
2015-12-08rl78: Enable MULU for all ISAs.DJ Delorie1-0/+5
2015-12-07Reorder some power9 insnsAlan Modra1-0/+5
2015-12-04Fix failures in the GAS testsuite for the ARC architecture.Claudiu Zissulescu1-0/+8
2015-12-02Fix ldah being disassembled as ldaexhAndre Vieira1-0/+5
2015-11-27[AArch64][PATCH 3/3] Add floating-point FP16 instructionsMatthew Wahab1-0/+18
2015-11-27[AArch64][PATCH 2/3] Adjust a utility function for floating point values.Matthew Wahab1-0/+10
2015-11-27[AArch64][PATCH 1/3] Support ARMv8.2 FP16 floating point instructions.Matthew Wahab1-0/+5
2015-11-27[AArch64] Add ARMv8.2 instruction alias REV64.Matthew Wahab1-0/+8
2015-11-27[AArch64] Add ARMv8.2 instructions BFC and REV64.Matthew Wahab1-0/+16
2015-11-27[AArch64] Let aliased instructions be their preferred form.Matthew Wahab1-0/+8
2015-11-27[Aarch64] Support an ARMv8.2 system register.Matthew Wahab1-0/+6
2015-11-23opcodes: handle mach-o for thumb/arm disambiguation.Tristan Gingold1-0/+4
2015-11-20[AArch64] Add support for ARMv8.1 Virtulization Host Extensions.Matthew Wahab1-0/+12
2015-11-20Remove a if-clause that is redundant because the same test has been performed...Nick Clifton1-0/+5
2015-11-20Update translations.Nick Clifton1-0/+4
2015-11-19[AArch64] Reject invalid immediate operands to MSR PANMatthew Wahab1-0/+5
2015-11-17Fix the disassembly of conditional instructions will illegal condition select...Nick Clifton1-0/+5
2015-11-14Bump version to 2.26.51Tristan Gingold1-0/+4
2015-11-11Add assembler, disassembler and linker support for power9.Peter Bergner1-0/+51
2015-11-02Disassemble RX NOP instructions as such.Nick Clifton1-0/+6
2015-11-02Fix disassembly of RX zero-offset register indirect instructions.Nick Clifton1-0/+7
2015-10-28Pass noaliases_p to aarch64_decode_insnYao Qi1-0/+8
2015-10-27Fix RL78 disassembly of DE+offset addressing to always show the offset, even ...Vinay Kumar1-0/+7
2015-10-27Display system registers by their names when disassembling RL78 instructions.Vinay Kumar1-0/+9
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