| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2015-07-16 | Updates the ARM disassembler's output of floating point constants to include ... | Alessandro Marzocchi | 1 | -0/+7 |
| 2015-07-14 | Sync config/warnings.m4 with GCC | H.J. Lu | 1 | -0/+4 |
| 2015-07-10 | Add missing changelog entries | Alan Modra | 1 | -0/+4 |
| 2015-07-03 | Remove ppc860, ppc750cl, ppc7450 insns from common ppc. | Alan Modra | 1 | -0/+6 |
| 2015-07-01 | Opcodes and assembler support for Nios II R2 | Sandra Loosemore | 1 | -0/+22 |
| 2015-06-30 | Add support for monitorx/mwaitx instructions | Amit Pawar | 1 | -0/+13 |
| 2015-06-22 | PPC sync instruction accepts invalid and incompatible operands | Peter Bergner | 1 | -0/+7 |
| 2015-06-22 | Stop "objdump -d" from disassembling past a symbolic address. | Nick Clifton | 1 | -0/+14 |
| 2015-06-19 | Allow for optional operands with non-zero default values. | Peter Bergner | 1 | -0/+11 |
| 2015-06-16 | [AArch64] Support id_mmfr4 system register | Matthew Wahab | 1 | -0/+4 |
| 2015-06-16 | Fixes a compile time warnng about left shifting a negative value. | Szabolcs Nagy | 1 | -0/+4 |
| 2015-06-12 | Remove unused MTMSRD_L macro and re-add accidentally deleted comment. | Peter Bergner | 1 | -0/+5 |
| 2015-06-04 | Fixes the check for emulated MSP430 instrucrtions that take no operands. | Nick Clifton | 1 | -0/+5 |
| 2015-06-02 | [ARM] Add support for ARMv8.1 PAN extension | Matthew Wahab | 1 | -0/+5 |
| 2015-06-02 | [ARM] Rework CPU feature selection in the disassembler | Matthew Wahab | 1 | -0/+5 |
| 2015-06-02 | [AArch64] Support for ARMv8.1a Adv.SIMD instructions | Matthew Wahab | 1 | -0/+9 |
| 2015-06-02 | [AArch64] Support for ARMv8.1a Limited Ordering Regions extension | Matthew Wahab | 1 | -0/+10 |
| 2015-06-01 | [AArch64][libopcode] Add support for PAN architecture extension | Matthew Wahab | 1 | -0/+8 |
| 2015-06-01 | x86/Intel: fix i386_optab[] for vcvt{,u}si2s{d,s} | Jan Beulich | 1 | -0/+4 |
| 2015-06-01 | x86/Intel: disassemble vcvt{,u}si2s{d,s} with correct operand order | Jan Beulich | 1 | -0/+5 |
| 2015-06-01 | x86/Intel: accept mandated operand order for vcvt{,u}si2s{d,s} | Jan Beulich | 1 | -0/+5 |
| 2015-05-18 | Remove Disp32 from AMD64 direct call/jmp | H.J. Lu | 1 | -0/+5 |
| 2015-05-15 | Support AMD64/Intel ISAs in assembler/disassembler | H.J. Lu | 1 | -0/+20 |
| 2015-05-14 | Fix some PPC assembler errors. | Peter Bergner | 1 | -0/+7 |
| 2015-05-13 | Add missing ChangeLog entries for PR binutis/18386 | H.J. Lu | 1 | -0/+13 |
| 2015-05-11 | Remove Disp16|Disp32 from 64-bit direct branches | H.J. Lu | 1 | -0/+7 |
| 2015-05-11 | Add Intel MCU support to opcodes | H.J. Lu | 1 | -0/+13 |
| 2015-04-30 | Make RL78 disassembler and simulator respect ISA for mul/div | DJ Delorie | 1 | -0/+15 |
| 2015-04-29 | Updated translations for various binutils components. | Nick Clifton | 1 | -0/+4 |
| 2015-04-27 | opcodes/ | Peter Bergner | 1 | -0/+14 |
| 2015-04-27 | S/390: Fixes for z13 instructions. | Andreas Krebbel | 1 | -0/+6 |
| 2015-04-23 | x86: disambiguate disassembly of certain AVX512 insns | Jan Beulich | 1 | -0/+7 |
| 2015-04-15 | Remove the unused PREFIX_UD_XXX | H.J. Lu | 1 | -0/+9 |
| 2015-04-15 | Check dp->prefix_requirement instead | H.J. Lu | 1 | -0/+6 |
| 2015-04-15 | Handle invalid prefixes for rdrand and rdseed | H.J. Lu | 1 | -0/+14 |
| 2015-04-15 | Replace mandatory_prefix with prefix_requirement | H.J. Lu | 1 | -0/+34 |
| 2015-04-15 | [ARM] Disassembles SSAT and SSAT16 instructions incorrectly for Thumb-2 | Renlin Li | 1 | -0/+6 |
| 2015-04-06 | x86: Use individual prefix control for each opcode. | Ilya Tocar | 1 | -0/+29 |
| 2015-03-30 | opcodes: d10v: fix old style prototype | Mike Frysinger | 1 | -0/+4 |
| 2015-03-29 | Add the missing opcodes/ChangeLog entry | H.J. Lu | 1 | -0/+4 |
| 2015-03-26 | powerpc: Only initialise opcode indices once | Anton Blanchard | 1 | -0/+5 |
| 2015-03-26 | powerpc: Add slbfee. instruction | Anton Blanchard | 1 | -0/+4 |
| 2015-03-24 | Extend arm_feature_set struct to provide more bits | Terry Guo | 1 | -0/+13 |
| 2015-03-17 | Add znver1 processor | Ganesh Gopalasubramanian | 1 | -0/+11 |
| 2015-03-13 | MIPS: Fix constraint issues with the R6 beqc and bnec instructions | Andrew Bennett | 1 | -0/+5 |
| 2015-03-13 | Add support for MIPS R6 evp and dvp instructions. | Andrew Bennett | 1 | -0/+4 |
| 2015-03-10 | S/390: Add more IBM z13 instructions | Andreas Krebbel | 1 | -0/+5 |
| 2015-03-10 | [AARCH64] Remove Load/Store register (unscaled immediate) alias. | Jiong Wang | 1 | -0/+9 |
| 2015-03-03 | [ARM] Skip private symbol when doing objdump | Jiong Wang | 1 | -0/+4 |
| 2015-02-25 | [SH] Fix clrs, sets, pref insn arch memberships. | Oleg Endo | 1 | -0/+7 |
