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2016-05-10Add support for ARMv8-M security extensions instructionsThomas Preud'homme1-0/+11
2016-05-09opcodes,gas: sparc: fix mnemonic of faligndataiJose E. Marchesi1-0/+4
2016-05-04[ARC] Add SYNTAX_NOP and SYNTAX_1OP for extension instructionsClaudiu Zissulescu1-0/+8
2016-05-03Fix generation of AArhc64 instruction table.Szabolcs Nagy1-0/+8
2016-04-28Add support to AArch64 disassembler for verifying instructions. Add verifier...Nick Clifton1-0/+9
2016-04-23Skip if size of bfd_vma is smaller than address sizeH.J. Lu1-0/+7
2016-04-20update many old style function definitionsTrevor Saunders1-0/+23
2016-04-19opcodes/arc: Add yet more nps instructionsAndrew Burgess1-0/+18
2016-04-19opcodes/arc: Add more nps instructionsAndrew Burgess1-0/+4
2016-04-15Regenerate Makefile.in/aclocal.m4 automake 1.11.6H.J. Lu1-0/+5
2016-04-14arc/nps400 : New cmem instructions and associated relocationAndrew Burgess1-0/+8
2016-04-14opcodes/arc: Move instruction length logic to new functionAndrew Burgess1-0/+6
2016-04-13Fix disassembly of the V850's LD.BU instruction.Nick Clifton1-0/+6
2016-04-12Add support for .extCondCode, .extCoreRegister and .extAuxRegister.Claudiu Zissulescu1-0/+14
2016-04-12Update ARC instruction data-base.Claudiu Zissulescu1-0/+4
2016-04-12Add support for .extInstruction pseudo-op.Claudiu Zissulescu1-19/+50
2016-04-11MIPS/opcodes: Fix undecoded MIPS16 extended instruction bit disassemblyMaciej W. Rozycki1-0/+5
2016-04-07arc/nps400: Add new instructionsAndrew Burgess1-0/+6
2016-04-07gas/arc: Handle multiple arc_opcode chains for same mnemonicAndrew Burgess1-0/+4
2016-04-05arc/nps400: Add additional instructionsAndrew Burgess1-0/+12
2016-04-05[ARC] Fix support for double assist instructions.Claudiu Zissulescu1-0/+9
2016-04-05[ARM] Add ARMv8.2 FP16 vmul/vmla/vmls (by scalar)Jiong Wang1-0/+4
2016-03-31opcodes: Fix date in ChangeLog entryAndrew Burgess1-1/+1
2016-03-31opcodes/arc/nps: Fix some operand flagsAndrew Burgess1-0/+5
2016-03-30opcodes/arc: Comment and whitespace fixes in opcode tableAndrew Burgess1-0/+5
2016-03-30[ARC] Cleanup AUX register names.Claudiu Zissulescu1-0/+9
2016-03-29[ARC] Fix typo in extension instruction name.Claudiu Zissulescu1-0/+4
2016-03-29[ARC] Add support for Quarkse opcodes.Claudiu Zissulescu1-0/+7
2016-03-24More -Wstack-usage warnings: opcodes/aarch64-*Jan Kratochvil1-0/+6
2016-03-24sparc: reorder wr instructions in sparc_opcodes to fix diagnosticsJose E. Marchesi1-0/+5
2016-03-22Add -Wstack-usage to the gcc warning flags list, but only if using a sufficie...Nick Clifton1-0/+4
2016-03-21arc/nps400: Add first nps400 instructionsAndrew Burgess1-0/+15
2016-03-21arc/opcodes: Use flag operand class to handle multiple flag matchesAndrew Burgess1-0/+5
2016-03-21arc: Add nps400 machine type, and assembler flag.Andrew Burgess1-0/+4
2016-03-21arc/gas: default mach is arc700, initialised in md_beginAndrew Burgess1-0/+4
2016-03-18Fix the disassembly of the AArch64's OOR instruction as a MOV instruction.Nick Clifton1-0/+6
2016-03-16[ARM] Support ARMv8.2 FP16 simd instructionsJiong Wang1-0/+4
2016-03-07Add const qualifiers at various places.Trevor Saunders1-0/+8
2016-03-03Regenerate or1k opcodes fileAlan Modra1-0/+1
2016-03-02Regenerate rl78 opcodes fileAlan Modra1-0/+1
2016-03-02Fix shift left warning at sourceAlan Modra1-0/+4
2016-03-01Fix typo in print_insn_rl78_common function.Nick Clifton1-0/+5
2016-02-24[OPCODES][ARM][1/3]Add armv8.2 fp16 instruction dissembler support.Renlin Li1-0/+5
2016-02-24[OPCODES][ARM]Fix mask for a few coprocessor opcodes.Renlin Li1-0/+5
2016-02-24[OPCODE][ARM]Correct disassembler for cdp/cdp2, mcr/mcr2, mrc/mrc2, ldc/ldc2,...Renlin Li1-0/+5
2016-02-15Add parentheses to prevent truncated addressesH.J. Lu1-0/+6
2016-02-10Add support for ARC instruction relaxation in the assembler.Claudiu Zissulescu1-0/+6
2016-02-04Fix the encoding of the MSP430's RRUX instruction.Nick Clifton1-0/+7
2016-02-02opcodes/cgen: Rework calculation of shift when inserting fieldsAndrew Burgess1-0/+17
2016-02-02epiphany/disassembler: Improve alignment of output.Andrew Burgess1-0/+4
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