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2006-11-102006-11-09 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu1-0/+5
* i386-dis.c (print_insn): Check PREFIX_REPNZ before PREFIX_DATA when prefix user table is used.
2006-11-102006-11-09 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu1-0/+15
* i386-dis.c (twobyte_uses_SSE_prefix): Renamed to ... (twobyte_uses_DATA_prefix): This. (twobyte_uses_REPNZ_prefix): New. (twobyte_uses_REPZ_prefix): Likewise. (threebyte_0x38_uses_DATA_prefix): Likewise. (threebyte_0x38_uses_REPNZ_prefix): Likewise. (threebyte_0x38_uses_REPZ_prefix): Likewise. (threebyte_0x3a_uses_DATA_prefix): Likewise. (threebyte_0x3a_uses_REPNZ_prefix): Likewise. (threebyte_0x3a_uses_REPZ_prefix): Likewise. (print_insn): Updated checking usages of DATA/REPNZ/REPZ prefixes.
2006-11-06 * ppc-opc.c: Restore COM to mfcr wrongly removed 2003-07-04.Alan Modra1-0/+4
2006-11-01* tc-score.c (do16_rdrs): Handle not! instruction especially.Nick Clifton1-0/+4
* score-opc.h (score_opcodes): Delete modifier '0x'. * gas/score/rD_rA.d: Correct not! and not.c instruction disassembly. * gas/score/b.d: Correct b! and b instruction disassembly.
2006-10-312006-10-30 Paul Brook <paul@codesourcery.com>Paul Brook1-0/+6
binutils/ * objdump.c (disassemble_section): Set info->symtab_pos. (disassemble_data): Set info->symtab and info->symtab_size. include/ * dis-asm.h (disassemble_info): Add symtab, symtab_pos and symtab_size. opcodes/ * arm-dis.c (last_is_thumb, last_mapping_sym, last_mapping_addr): New. (get_sym_code_type): New function. (print_insn): Search for mapping symbols.
2006-10-31* tc-score.c (data_op2): Check invalid operands.Nick Clifton1-0/+5
(my_get_expression): Const operand of some instructions can not be symbol in assembly. (get_insn_class_from_type): Handle instruction type Insn_internal. (do_macro_ldst_label): Modify inst.type. (Insn_PIC): Delete. * score-inst.h (enum score_insn_type): Add Insn_internal. * tc-score.c (data_op2): The immediate value in lw is 15 bit signed. * score-dis.c (print_insn): Correct the error code to print correct PCE instruction disassembly.
2006-10-262006-10-26 Ben Elliston <bje@au.ibm.com>Peter Bergner1-0/+28
Anton Blanchard <anton@samba.org> Peter Bergner <bergner@vnet.ibm.com> * ppc-opc.c (A_L, DCM, DGM, TE, RMC, R, SP, S, SH16, XRT_L, EH, AFRALFRC_MASK, Z, ZRC, Z_MASK, XLRT_MASK, XEH_MASK): Define. (POWER6): Define. (powerpc_opcodes): Extend "lwarx", "ldarx", "dcbf", "fres", "fres.", "frsqrtes", "frsqrtes." "fre", "fre.", "frsqrte" and "frsqrte.". Add "doze", "nap", "sleep", "rvwinkle", "dcbfl", "prtyw", "prtyd", "mfcfar", "cmpb", "lfdpx", "stfdpx", "mtcfar", "mffgpr", "mftgpr", "lwzcix", "lhzcix", "lbzcix", "ldcix", "lfiwax", "stwcix", "sthcix", "stbcix", "stdcix", "lfdp", "dadd", "dadd.", "dqua", "dqua.", "dmul", "dmul.", "drrnd", "drrnd.", "dscli", "dscli.", "dquai", "dquai.", "dscri", "dscri.", "drintx", "drintx.", "dcmpo", "dtstex", "dtstdc", "dtstdg", "dtstsf", "drintn", "drintn.", "dctdp", "dctdp.", "dctfix", "dctfix.", "ddedpd", "ddedpd.", "dxex", "dxex.", "dsub", "dsub.", "ddiv", "ddiv.", "dcmpu", "drsp", "drsp.", "dcffix", "dcffix.", "denbcd", "denbcd.", "diex", "diex.", "stfdp", "daddq", "daddq.", "dquaq", "dquaq.", "fcpsgn", "fcpsgn.", "dmulq", "dmulq.", "drrndq", "drrndq.", "dscliq", "dscliq.", "dquaiq", "dquaiq.", "dscriq", "dscriq.", "drintxq", "drintxq.", "dcmpoq", "dtstexq", "dtstdcq", "dtstdgq", "dtstsfq", "drintnq", "drintnq.", "dctqpq", "dctqpq.", "dctfixq", "dctfixq.", "ddedpdq", "ddedpdq.", "dxexq", "dxexq.", "dsubq", "dsubq.", "ddivq", "ddivq.", "dcmpuq", "drdpq", "drdpq.", "dcffixq", "dcffixq.", "denbcdq", "denbcdq.", "diexq" and "diexq." opcodes.
2006-10-26 * h8300-dis.c (bfd_h8_disassemble): Add missing consts.Daniel Jacobowitz1-0/+4
2006-10-25New Cell SPU port.Alan Modra1-0/+15
2006-10-24Add powerpc cell support.Alan Modra1-0/+8
2006-10-23Fix AMDFAM10 POPCNT instructionMichael Meissner1-0/+7
2006-10-202006-10-20 Andrew Stubbs <andrew.stubbs@st.com>Andrew Stubbs1-0/+5
opcodes/ * sh-dis.c (print_insn_sh): Remove 0x from output to prevent GDB duplicating it. gas/testsuite/ * gas/sh/pcrel-coff.d: Update patterns (remove 0x on addresses). * gas/sh/pcrel-hms.d: Likewise. * gas/sh/pcrel.d: Likewise. * gas/sh/pcrel2.d: Likewise. * gas/sh/pic.d: Likewise. * gas/sh/tlsd.d: Likewise. * gas/sh/tlsdnopic.d: Likewise. * gas/sh/tlsdpic.d: Likewise.
2006-10-182006-10-18 Dave Brolley <brolley@redhat.com>Dave Brolley1-1/+5
* configure.in (BFD_MACHINES): Add cgen-bitset.lo for bfd_sh_arch. * configure: Regenerated.
2006-09-29Regenerate.Alan Modra1-0/+4
2006-09-26bfd/Joseph Myers1-0/+14
2006-09-26 Mark Shinwell <shinwell@codesourcery.com> Joseph Myers <joseph@codesourcery.com> Ian Lance Taylor <ian@wasabisystems.com> Ben Elliston <bje@wasabisystems.com> * archures.c: Add definition for bfd_mach_arm_iWMMXt2. * cpu-arm.c (processors): Add bfd_mach_arm_iWMMXt2. (arch_info_struct, bfd_arm_update_notes): Likewise. (architectures): Likewise. (bfd_arm_merge_machines): Check for iWMMXt2. * bfd-in2.h: Rebuild. gas/ 2006-09-26 Mark Shinwell <shinwell@codesourcery.com> Joseph Myers <joseph@codesourcery.com> Ian Lance Taylor <ian@wasabisystems.com> Ben Elliston <bje@wasabisystems.com> * config/tc-arm.c (arm_cext_iwmmxt2): New. (enum operand_parse_code): New code OP_RIWR_I32z. (parse_operands): Handle OP_RIWR_I32z. (do_iwmmxt_wmerge): New function. (do_iwmmxt_wldstd): Handle iwmmxt2 case where second operand is a register. (do_iwmmxt_wrwrwr_or_imm5): New function. (insns): Mark instructions as RIWR_I32z as appropriate. Also add torvsc<b,h,w>, wabs<b,h,w>, wabsdiff<b,h,w>, waddbhus<l,m>, waddhc, waddwc, waddsubhx, wavg4{r}, wmaddu{x,n}, wmadds{x,n}, wmerge, wmiaxy{n}, wmiawxy{n}, wmul<sm,um>{r}, wmulw<um,sm,l>{r}, wqmiaxy{n}, wqmulm{r}, wqmulwm{r}, wsubaddhx. (md_begin): Handle IWMMXT2. (arm_cpus): Add iwmmxt2. (arm_extensions): Likewise. (arm_archs): Likewise. gas/testsuite/ 2006-09-26 Mark Shinwell <shinwell@codesourcery.com> Joseph Myers <joseph@codesourcery.com> Ian Lance Taylor <ian@wasabisystems.com> Ben Elliston <bje@wasabisystems.com> * gas/arm/iwmmxt2.s: New file. * gas/arm/iwmmxt2.d: New file. include/opcode/ 2006-09-26 Mark Shinwell <shinwell@codesourcery.com> Joseph Myers <joseph@codesourcery.com> Ian Lance Taylor <ian@wasabisystems.com> Ben Elliston <bje@wasabisystems.com> * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define. opcodes/ 2006-09-26 Mark Shinwell <shinwell@codesourcery.com> Joseph Myers <joseph@codesourcery.com> Ian Lance Taylor <ian@wasabisystems.com> Ben Elliston <bje@wasabisystems.com> * arm-dis.c (coprocessor_opcodes): The X-qualifier to WMADD may only be used with the default multiply-add operation, so if N is set, don't bother printing X. Add new iwmmxt instructions. (IWMMXT_INSN_COUNT): Update. (iwmmxt_wwssnames): Qualify "wwss" names at index 2, 6, 10 and 14 with a 'c' suffix. (print_insn_coprocessor): Check for iWMMXt2. Handle format specifiers 'r', 'i'.
2006-09-242006-09-24 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>H.J. Lu1-0/+7
PR binutils/3100 * i386-dis.c (prefix_user_table): Fix the second operand of maskmovdqu instruction to allow only %xmm register instead of both %xmm register and memory.
2006-09-24Add PR binutils/3000 to its entry.H.J. Lu1-0/+1
2006-09-23gas/H.J. Lu1-0/+6
2006-09-23 H.J. Lu <hongjiu.lu@intel.com> PR binutils/3235 * config/tc-i386.c (match_template): Check address size prefix to turn Disp64/Disp32/Disp16 operand into Disp32/Disp16/Disp32 operand. gas/testsuite/ 2006-09-23 H.J. Lu <hongjiu.lu@intel.com> PR binutils/3235 * gas/i386/addr16.d: New file. * gas/i386/addr16.s: Likewise. * gas/i386/addr32.d: Likewise. * gas/i386/addr32.s: Likewise. * gas/i386/i386.exp: Add "addr16" and "addr32". * gas/i386/x86-64-addr32.s: Add tests for "add32 mov". * gas/i386/x86-64-addr32.d: Updated. opcodes/ 2006-09-23 H.J. Lu <hongjiu.lu@intel.com> PR binutils/3235 * i386-dis.c (OP_OFF64): Get 32bit offset if there is an address size prefix.
2006-09-16Add support for Score target.Nick Clifton1-0/+10
2006-09-16* bfd-in.h (STRING_AND_COMMA): New macro. Takes one constant string as itsNick Clifton1-0/+11
argument and emits the string followed by a comma and then the length of the string. (CONST_STRNEQ): New macro. Checks to see if a variable string has a constant string as its initial characters. (CONST_STRNCPY): New macro. Copies a constant string to the start of a variable string. * bfd-in2.h: Regenerate. * <remainign files>: Make use of the new macros.
2006-09-052006-09-04 Paul Brook <paul@codesourcery.com>Paul Brook1-0/+4
gas/ * config/tc-arm.c (do_neon_dyadic_if_i): Remove. (do_neon_dyadic_if_i_d): Avoid setting U bit. (do_neon_mac_maybe_scalar): Ditto. (do_neon_dyadic_narrow): Force operand type to NT_integer. (insns): Remove out of date comments. gas/testsuite/ * gas/arm/neon-cov.s: Test .u and .s aliases for .i suffixes. * gas/arm/neon-cov.d: Adjust expected output. opcodes/ * arm-dis.c (neon_opcode): Fix suffix on VMOVN.
2006-08-232006-08-23 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu1-2/+6
* i386-dis.c (three_byte_table): Expand to 256 elements.
2006-08-14Fix bug 3000Michael Meissner1-0/+10
2006-07-29opcodes/Richard Sandiford1-0/+5
* m68k-opc.c (m68k_opcodes): Fix operand specificer in the Coldfire "fdaddl" entry. gas/testsuite/ * gas/m68k/mcf-fpu.s: Add tests for all addressing modes. * gas/m68k/mcf-fpu.d: Update accordingly.
2006-07-192006-07-19 Paul Brook <paul@codesourcery.com>Paul Brook1-0/+4
gas/ * config/tc-arm.c (insns): Fix rbit Arm opcode. gas/testsuite/ * gas/arm/archv6t2.d: Adjust expected output for rbit. opcodes/ * armd-dis.c (arm_opcodes): Fix rbit opcode.
2006-07-18gas/testsuite/H.J. Lu1-0/+5
2006-07-18 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/opcode.s: Add sldt, smsw and str. * gas/i386/x86-64-opcode.s: Likewise. * gas/i386/opcode.d: Updated. * gas/i386/x86-64-opcode.d: Likewise. opcodes/ 2006-07-18 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (grps): Change "sldtQ", "strQ" and "smswQ" to "sldt", "str" and "smsw".
2006-07-15Add missing ChangeLog entry.H.J. Lu1-0/+17
2006-07-13Add amdfam10 instructionsMichael Meissner1-0/+10
2006-07-05 * arm-dis.c (coprocessor): Alter fmsrr disassembly syntax.Julian Brown1-0/+4
2006-06-12gas/testsuite/H.J. Lu1-0/+5
2006-06-12 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run nops and x86-64-nops. * gas/i386/nops.d: New file. * gas/i386/nops.s: Likewise. * gas/i386/x86-64-nops.d: Likewise. * gas/i386/x86-64-nops.s: Likewise. include/opcode/ 2006-06-12 H.J. Lu <hongjiu.lu@intel.com> * i386.h (i386_optab): Add "nop" with memory reference. opcodes/ 2006-06-12 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (dis386_twobyte): Use "nopQ" for 0x1f. (twobyte_has_modrm): Set 1 for 0x1f.
2006-06-12gas/H.J. Lu1-0/+7
2006-06-12 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (process_suffix): Don't add rex64 for "xchg %rax,%rax". gas/testsuite/ 2006-06-12 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/opcode.s: Add "xchg %ax,%ax". * gas/i386/opcode.d: Updated. * gas/i386/x86-64-opcode.s: Add xchg %ax,%ax, xchg %eax,%eax, xchg %rax,%rax, rex64 xchg %rax,%rax and xchg %rax,%r8. * gas/i386/x86-64-opcode.d: Updated. include/opcode/ 2006-06-12 H.J. Lu <hongjiu.lu@intel.com> * i386.h (i386_optab): Update comment for 64bit NOP. opcodes/ 2006-06-12 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (NOP_Fixup): Removed. (NOP_Fixup1): New. (NOP_Fixup2): Likewise. (dis386): Use NOP_Fixup1 and NOP_Fixup2 on 0x90.
2006-06-12 * arm-dis.c (print_insn_neon): Disassemble 32-bit immediates as signedJulian Brown1-0/+5
on 64-bit hosts.
2006-06-102006-06-10 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu1-0/+15
* i386.c (GRP10): Renamed to ... (GRP12): This. (GRP11): Renamed to ... (GRP13): This. (GRP12): Renamed to ... (GRP14): This. (GRP13): Renamed to ... (GRP15): This. (GRP14): Renamed to ... (GRP16): This. (dis386_twobyte): Updated. (grps): Likewise.
2006-06-09Updated Finnish translationNick Clifton1-0/+4
2006-06-07bfd/doc:Joseph Myers1-0/+4
* bfd.texinfo: Remove local @tex code. bfd: * po/Make-in (pdf, ps): New dummy targets. binutils: * po/Make-in (pdf, ps): New dummy targets. gas: * po/Make-in (pdf, ps): New dummy targets. gprof: * po/Make-in (pdf, ps): New dummy targets. ld: * po/Make-in (pdf, ps): New dummy targets. opcodes: * po/Make-in (pdf, ps): New dummy targets.
2006-06-072006-06-06 Paul Brook <paul@codesourcery.com>Paul Brook1-0/+17
opcodes/ * arm-dis.c (coprocessor_opcodes): Add %c to unconditional arm instructions. (neon_opcodes): Add conditional execution specifiers. (thumb_opcodes): Ditto. (thumb32_opcodes): Ditto. (arm_conditional): Change 0xe to "al" and add "" to end. (ifthen_state, ifthen_next_state, ifthen_address): New. (IFTHEN_COND): Define. (print_insn_coprocessor, print_insn_neon): Print thumb conditions. (print_insn_arm): Change %c to use new values of arm_conditional. (print_insn_thumb16): Print thumb conditions. Add %I. (print_insn_thumb32): Print thumb conditions. (find_ifthen_state): New function. (print_insn): Track IT block state. gas/testsuite/ * gas/arm/thumb2_bcond.d: Update expected output. * gas/arm/thumb32.d: Ditto. * gas/arm/vfp1_t2.d: Ditto. * gas/arm/vfp1xD_t2.d: Ditto. binutils/testsuite/ * binutils-all/arm/objdump.exp: New file. * binutils-all/arm/thumb2-cond.s: New test.
2006-06-07include/opcode/Alan Modra1-0/+7
* ppc.h (PPC_OPCODE_POWER6): Define. Adjust whitespace. gas/ * config/tc-ppc.c (parse_cpu): Handle "-mpower6". (md_show_usage): Document it. (ppc_setup_opcodes): Test power6 opcode flag bits. * doc/c-ppc.texi (PowerPC-Opts): Document "-mpower6". opcodes/ * ppc-dis.c (powerpc_dialect): Handle power6 option. (print_ppc_disassembler_options): Mention power6.
2006-06-06 [ gas/ChangeLog ]Thiemo Seufer1-0/+6
* config/tc-mips.c (ISA_SUPPORTS_DSP64): New macro. (CPU_HAS_MIPS3D, CPU_HAS_MDMX, CPU_HAS_DSP, CPU_HAS_MT): Delete. (macro_build): Update comment. (mips_ip): Allow DSP64 instructions for MIPS64R2. (mips_after_parse_args): Remove uses of CPU_HAS_MIPS3D and CPU_HAS_MDMX. (mips_cpu_info): Fix formatting. Add MIPS_CPU_ASE_MIPS3D and MIPS_CPU_ASE_MDMX flags for sb1. [ gas/testsuite/ChangeLog ] * gas/mips/mips64-dsp.s, gas/mips/mips64-dsp.d: New DSP64 tests. * gas/mips/mips.exp: Run DSP64 tests. [ opcodes/ChangeLog ] * mips-dis.c: Disassemble DSP64 instructions for MIPS64R2. * mips-opc.c: Add DSP64 instructions.
2006-06-06 * m68hc11-dis.c (print_insn): Warning fix.Alan Modra1-0/+4
2006-06-05bfd/, binutils/, gas/, gprof/, ld/, opcodes/Daniel Jacobowitz1-0/+4
* po/Make-in (top_builddir): Define.
2006-06-05 * Makefile.am: Run "make dep-am".Alan Modra1-0/+6
* Makefile.in: Regenerate. * config.in: Regenerate.
2006-05-31Configury changes: update src repository (binutils, gdb, and rda) to useDaniel Jacobowitz1-0/+8
config/gettext-sister.m4 instead of the old gettext.m4. Regenerate all affected autotools files. Include intl in gdb releases again.
2006-05-30Update Spanish translationNick Clifton1-0/+4
2006-05-25include/opcodes/Richard Sandiford1-0/+11
* m68k.h (mcf_mask): Define. opcodes/ * m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd and fmovem entries. Put register list entries before immediate mask entries. Use "l" rather than "L" in the fmovem entries. * m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it out from INFO. (m68k_scan_mask): New function, split out from... (print_insn_m68k): ...here. If no architecture has been set, first try printing an m680x0 instruction, then try a Coldfire one. gas/testsuite/ * gas/m68k/mcf-fpu.s: Add fmovemd and fmovem instructions. * gas/m68k/mcf-fpu.d: Adjust accordingly.
2006-05-24Updated Vietnamese and Irish translationsNick Clifton1-0/+4
2006-05-22* crx-dis.c (EXTRACT): Make macro work on 64-bit hosts.Nick Clifton1-0/+4
2006-05-22Updated Dutch translationNick Clifton1-0/+4
2006-05-22Remove ChangeLog entries, since the template files were already up to date.Nick Clifton1-4/+0
2006-05-22Update translation templatesNick Clifton1-0/+4
2006-05-17 * avr-dis.c: Formatting fix.Alan Modra1-0/+4
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