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AgeCommit message (Expand)AuthorFilesLines
2016-12-20Correct assembler mnemonic for RISC-V aqrl AMOsAndrew Waterman1-0/+5
2016-12-20Fix disassembly of RISC-V CSR instructions under -Mno-aliasesAndrew Waterman1-0/+5
2016-12-20Add canonical JALR for RISC-VAndrew Waterman1-0/+5
2016-12-20Re-work RISC-V gas flags: now we just support -mabi and -marchAndrew Waterman1-0/+5
2016-12-20Formatting changes for RISC-VAndrew Waterman1-0/+4
2016-12-20Add opcodes RISC-V dependenciesAlan Modra1-0/+6
2016-12-19MIPS/opcodes: Only examine ELF file structures if SYMTAB_AVAILABLEMaciej W. Rozycki1-0/+5
2016-12-19MIPS/opcodes: Only call `bfd_mips_elf_get_abiflags' if BFD64Maciej W. Rozycki1-0/+5
2016-12-16Fix compile time warning building arm-dis.cNick Clifton1-0/+5
2016-12-14MIPS/opcodes: Also set disassembler's ASE flags from ELF structuresMaciej W. Rozycki1-0/+6
2016-12-14MIPS/opcodes: Reorder ELF file header flag handling in disassemblerMaciej W. Rozycki1-0/+5
2016-12-14MIPS16: Fix SP-relative SD instruction annotationMaciej W. Rozycki1-0/+5
2016-12-14MIPS16/opcodes: Fix and clarify MIPS16e commentaryMaciej W. Rozycki1-0/+5
2016-12-13[Binutils][AARCH64]Remove Cn register for coprocessor CRn, CRm fieldRenlin Li1-0/+13
2016-12-12Handle memory error in print_insn_rxYao Qi1-0/+8
2016-12-12Handle memory error in print_insn_rl78_commonYao Qi1-0/+8
2016-12-09MIPS16: Remove unused `>' operand codeMaciej W. Rozycki1-0/+4
2016-12-09MIPS16/opcodes: Use hexadecimal interpretation for the `e' operand codeMaciej W. Rozycki1-0/+5
2016-12-09MIPS16/opcodes: Reformat raw EXTEND and undecoded outputMaciej W. Rozycki1-0/+7
2016-12-08MIPS16/opcodes: Fix off-by-one indentation in `print_mips16_insn_arg'Maciej W. Rozycki1-0/+5
2016-12-08MIPS16/opcodes: Fix PC-relative operation delay-slot adjustmentMaciej W. Rozycki1-0/+6
2016-12-08AArch64/opcodes: Correct another `index' global shadowing errorMaciej W. Rozycki1-0/+5
2016-12-08Fix crash when disassembling invalid range on powerpc vleLuis Machado1-0/+4
2016-12-07MIPS/opcodes: Correct an `interaction' comment typoMaciej W. Rozycki1-0/+4
2016-12-07MIPS16/opcodes: Update opcode table commentMaciej W. Rozycki1-0/+5
2016-12-07MIPS/opcodes: Reformat `-M' disassembler option's help textMaciej W. Rozycki1-0/+4
2016-12-05[ARM] Add ARMv8.3 VCMLA and VCADD instructionsSzabolcs Nagy1-0/+5
2016-12-05[ARM] Add ARMv8.3 VJCVT instructionSzabolcs Nagy1-0/+4
2016-12-01Fix abort in x86 disassembler.Nick Clifton1-0/+6
2016-11-29[ARC] Add checking for LP_COUNT reg usage, improve error reporting.Claudiu Zissulescu1-0/+46
2016-11-29[ARC] Fix disassembler option.Claudiu Zissulescu1-0/+8
2016-11-28X86: Ignore REX_B bit for 32-bit XOP instructionsAmit Pawar1-0/+7
2016-11-22Fix spelling mistakes in comments in configure scriptsAmbrogino Modigliani1-0/+4
2016-11-22gas,opcodes: fix hardware capabilities bumping in the sparc assembler.Jose E. Marchesi1-0/+16
2016-11-22[ARC] Fix printing 'b' mnemonics.Claudiu Zissulescu1-0/+5
2016-11-18[AArch64] Add ARMv8.3 FCMLA and FCADD instructionsSzabolcs Nagy1-0/+18
2016-11-18[AArch64] Add ARMv8.3 weaker release consistency load instructionsSzabolcs Nagy1-0/+7
2016-11-18[AArch64] Add ARMv8.3 javascript floating-point conversion instructionSzabolcs Nagy1-0/+8
2016-11-18[AArch64] Add ARMv8.3 combined pointer authentication load instructionsSzabolcs Nagy1-0/+17
2016-11-11[AArch64] Add ARMv8.3 combined pointer authentication branch instructionsSzabolcs Nagy1-0/+8
2016-11-11[AArch64] Add ARMv8.3 PACGA instructionSzabolcs Nagy1-0/+9
2016-11-11[AArch64] Add ARMv8.3 single source PAC instructionsSzabolcs Nagy1-0/+9
2016-11-11[AArch64] Add ARMv8.3 pointer authentication key registersSzabolcs Nagy1-0/+7
2016-11-11[AArch64] Add ARMv8.3 instructions which are in the NOP spaceSzabolcs Nagy1-0/+9
2016-11-11[AArch64] Increase max_num_aliases in aarch64-genSzabolcs Nagy1-0/+4
2016-11-09X86: Remove the .s suffix from EVEX vpextrwH.J. Lu1-0/+14
2016-11-09Update opcodes/ChangeLogH.J. Lu1-0/+1
2016-11-09X86: Merge AVX512F vmovqH.J. Lu1-0/+4
2016-11-08X86: Remove the THREE_BYTE_0F7A entryH.J. Lu1-0/+7
2016-11-07X86: Properly handle bad FPU opcodeH.J. Lu1-0/+14
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