Age | Commit message (Collapse) | Author | Files | Lines |
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(print_insn_ppi): Make nib1, nib2, nib3 unsigned.
Initialize variable dc to NULL.
(print_insn_shx): Remove unused label d_reg_n.
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print_insn_cris_with_register_prefix.
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* cgen-dis.in (print_insn): All insns which can fit into insn_value
must be loaded there in their entirety.
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* config/tc-sparc.c (sparc_ip): Fix a bug which caused v9_arg_p
instructions to loose any special insn->architecture mask.
* config/tc-sparc.c (v9a_asr_table): Add v9b ASRs.
(sparc_md_end, sparc_arch_types, sparc_arch,
sparc_elf_final_processing): Handle v8plusb and v9b architectures.
(sparc_ip): Handle siam mode operands. Support v9b ASRs (and
request v9b architecture if they are used).
bfd/
* elf32-sparc.c (elf32_sparc_merge_private_bfd_data,
elf32_sparc_object_p, elf32_sparc_final_write_processing):
Support v8plusb.
* elf64-sparc.c (sparc64_elf_merge_private_bfd_data,
sparc64_elf_object_p): Support v9b.
* archures.c: Declare v8plusb and v9b machines.
* bfd-in2.h: Ditto.
* cpu-sparc.c: Ditto.
include/opcode/
* sparc.h (enum sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_V9B.
Note that '3' is used for siam operand.
opcodes/
* sparc-dis.c (v9a_asr_reg_names): Add v9b ASRs.
(compute_arch_mask): Add v8plusb and v9b machines.
(print_insn_sparc): siam mode decoding, accept ASRs up to 25.
* opcodes/sparc-opc.c: Support for Cheetah instruction set.
(prefetch_table): Add #invalidate.
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* fr30-desc.h: Regenerate.
* m32r-desc.h: Regenerate.
* m32r-ibld.c: Regenerate.
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* config/tc-ia64.c (resources_match): Handle IA64_RS_PRr.
* ia64-ic.tbl: Update from Intel.
* ia64-asmtab.c: Regenerate.
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* ia64-gen.c: Convert C++-style comments to C-style comments.
* tic54x-dis.c: Likewise.
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don't have a leading underscore. Fix formatting.
* cris-dis.c (REGISTER_PREFIX_CHAR): New.
(format_reg): Add parameter with_reg_prefix. All callers changed.
(print_with_operands): Ditto.
(print_insn_cris_generic): Renamed from print_insn_cris, add
parameter with_reg_prefix.
(print_insn_cris_with_register_prefix,
print_insn_cris_without_register_prefix, cris_get_disassembler):
New.
* disassemble.c (disassembler) [ARCH_cris]: Call cris_get_disassembler.
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* gas/ia64/opc-f.pl: Add missing fcmp and fpcmp tests.
* gas/ia64/opc-f.s, gas/ia64/opc-f.d: Regenerate.
* ia64-opc-f.c (ia64_opcodes_f): Add fpcmp pseudo-ops for
gt, ge, ngt, and nge.
* ia64-asmtab.c: Regenerate.
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gas/ChangeLog
* config/tc-ia64.c (dv_sem): Add "stop".
(specify_resource, case IA64_RS_PR): Only handles regs 1 to 15 now.
(specify_resource, case IA64_RS_PRr): New for regs 16 to 62.
(specify_resource, case IA64_RS_PR63): Reorder (note == 7) test to
match above.
(mark_resources): Check IA64_RS_PRr.
gas/testsuite/ChangeLog
* gas/ia64/dv-raw-err.s: Add new testcases for PR%, 16 - 62.
* gas/ia64/dv-waw-err.s: Likewise.
* gas/ia64/dv-imply.d: Regenerate.
* gas/ia64/dv-mutex.d, gas/ia64/dv-raw-err.l, gas/ia64/dv-safe.d,
gas/ia64/dv-srlz.d, gas/ia64/dv-war-err.l, gas/ia64/dv-waw-err.l,
gas/ia64/opc-f.d, gas/ia64/opc-i.d, gas/ia64/opc-m.d: Likewise.
include/opcode/ChangeLog
* ia64.h (enum ia64_dependency_semantics): Add IA64_DVS_STOP.
opcodes/ChangeLog
* ia64-dis.c (print_insn_ia64): Revert Aug 7 byte skip count change.
* ia64-gen.c (parse_semantics): Handle IA64_DVS_STOP.
(lookup_specifier): Handle "PR%, 1 to 15" and "PR%, 16 to 62".
* ia64-ic.tbl, ia64-raw.tbl, ia64-war.tbl, ia64-waw.tbl: Update.
* ia64-asmtab.c: Regnerate.
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* d30v-opc.c (d30v_operand_t): New operand type Rb2.
(d30v_format_tab): Use Rb2 for modinc and moddec.
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modinc and moddec.
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top level.
* aclocal.m4, configure: Rebuilt.
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2000-08-30 Mark Hatle <mhatle@mvista.com>
* config/tc-ppc.c (md_parse_option): Recognize -m405.
In src/opcodes/ChangeLog:
2000-08-30 Mark Hatle <mhatle@mvista.com>
* ppc-opc.c Add XTLB macro for a few PPC 4xx extended mnemonics.
(powerpc_opcodes): Add table entries for PPC 405 instructions.
Changed rfci, icbt, mfdcr, dccci, mtdcr, iccci from PPC to PPC403
instructions.
Added extended mnemonic mftbl as defined in the 405GP manual
for all PPCs.
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* tic80-dis.c: Fix formatting.
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* w65-dis.c: Fix formatting.
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* ia64-dis.c (print_insn_ia64): Add failed label after ia64_free_opcode
call. Change last goto to use failed instead of done.
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* cgen-ibld.in (cgen_put_insn_int_value): New function.
(insert_normal): Allow for non-zero word_offset with CGEN_INT_INSN_P.
(insert_insn_normal): Use cgen_put_insn_int_value with CGEN_INT_INSN_P.
(extract_normal): Allow for non-zero word_offset with CGEN_INT_INSN_P.
* cgen-dis.in (read_insn): New static function.
(print_insn): Use read_insn to read the insn into the buffer and set
up for disassembly.
(print_insn): in CGEN_INT_INSN_P, make sure that the entire insn is
in the buffer.
* fr30-asm.c: Regenerated.
* fr30-desc.c: Regenerated.
* fr30-desc.h Regenerated.
* fr30-dis.c: Regenerated.
* fr30-ibld.c: Regenerated.
* fr30-opc.c: Regenerated.
* fr30-opc.h Regenerated.
* m32r-asm.c: Regenerated.
* m32r-desc.c: Regenerated.
* m32r-desc.h Regenerated.
* m32r-dis.c: Regenerated.
* m32r-ibld.c: Regenerated.
* m32r-opc.c: Regenerated.
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* tic30-dis.c: Fix formatting.
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* sh-dis.c: Fix formatting.
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* ppc-opc.c (powerpc_opcodes): Add rfid, mtsrd, mtsrdin, mtmsrd.
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* z8k-dis.c: Fix formatting.
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gas/
* config/tc-ia64.c (specify_resource, case IA64_RS_GR): Handle
postincrement modified registers. Handle IA64_OPND_R3_2 addl
source registers.
(note_register_values): Handle IA64_OPND_R3_2 operands.
gas/testsuite/
* gas/ia64/dv-raw-err.s: Add new tests for addl and postinc.
* gas/ia64/dv-raw-err.l: Likewise.
* gas/ia64/dv-waw-err.l: Update sed pattern.
* gas/ia64/opc-f.pl: Delete fpsub, and fpadd comment.
* gas/ia64/opc-f.s, gas/ia64/opc-f.d: Regenerate.
include/opcode/
* ia64.h (IA64_OPCODE_POSTINC): New.
opcodes/
* ia64-ic.tbl (pr-readers-nobr-nomovpr): Add addl, adds. Delete
break, mov-immediate, nop.
* ia64-opc-f.c: Delete fpsub instructions.
* ia64-opc-m.c: Add POSTINC to all instructions with postincrement
address operand. Rewrite using macros to avoid long lines.
* ia64-opc.h (POSTINC): Define.
* ia64-asmtab.c: Regenerate.
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* ia64-ic.tbl: Add missing entries.
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* i860-dis.c (print_br_address): Change third argument from int
to long.
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for MLI templates. Handle IA64_OPND_TGT64.
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Change return type from void to int. Check the combination
of operands, return 1 if valid. Fix to avoid BUF overflow.
Report undefined combinations of operands in COMMENT.
Report internal errors to stderr. Output the adiw/sbiw
constant operand in both decimal and hex.
(print_insn_avr): Disassemble ldd/std with displacement of 0
as ld/st. Check avr_operand () return value, handle invalid
combinations of operands like unknown opcodes.
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* cgen-dis.in, cgen-asm.in, cgen-ibld.in: New files.
* cgen.sh: Likewise.
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gas/
* config/tc-ia64.c (emit_one_bundle): Call ia64_free_opcode
before ia64_find_opcode.
(md_assemble): Likewise.
opcodes/
* ia64-dis.c (print_insn_ia64): Call ia64_free_opcode at end.
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* Makefile.am (CGEN, CGENDEPS, CGENDIR, CGENFLAGS): New.
(run-cgen, stamp-m32r, stamp-fr30): New targets.
* Makefile.in: Regenerate.
* configure.in: Add --enable-cgen-maint option.
* configure: Regenerate.
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