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AgeCommit message (Expand)AuthorFilesLines
2018-04-26x86: fold various non-memory operand AVX512VL templatesJan Beulich1-0/+6
2018-04-26x86: CpuXSAVE is a prereq for various other featuresJan Beulich1-0/+8
2018-04-26x86: drop CpuRegMMX, CpuReg[XYZ]MM, and CpuRegMaskJan Beulich1-0/+16
2018-04-26x86: x87-related adjustmentsJan Beulich1-0/+6
2018-04-26x86: drop VexImmExtJan Beulich1-0/+7
2018-04-25x86: drop redundant AVX512VL shift templatesJan Beulich1-0/+6
2018-04-25Fix the mask for the sqrdml(a|s)h instructions.Tamar Christina1-0/+4
2018-04-17Enable Intel CLDEMOTE instruction.Igor Tsimbalist1-0/+12
2018-04-16Remove sh5 and sh64 supportAlan Modra1-0/+14
2018-04-16Remove w65 supportAlan Modra1-0/+12
2018-04-16Remove we32k supportAlan Modra1-0/+5
2018-04-16Remove m88k supportAlan Modra1-0/+11
2018-04-16Remove i370 supportAlan Modra1-0/+12
2018-04-16Remove h8500 supportAlan Modra1-0/+12
2018-04-16Remove tahoe supportAlan Modra1-0/+5
2018-04-15x86: Allow 32-bit registers for tpause and umwaitH.J. Lu1-0/+8
2018-04-11Enable Intel WAITPKG instructions.Igor Tsimbalist1-0/+16
2018-04-11Remove i860, i960, bout and aout-adobe targetsAlan Modra1-0/+12
2018-04-04i386: Clear vex instead of vex.evexH.J. Lu1-0/+7
2018-04-04Update Spanish translations for ld/ opcodes/ and gold/ sub-directoriesNick Clifton1-0/+4
2018-03-28x86: drop VecESizeJan Beulich1-0/+8
2018-03-28x86: convert broadcast insn attribute to booleanJan Beulich1-0/+8
2018-03-28x86: fold to-scalar-int conversion insnsJan Beulich1-0/+6
2018-03-28x86: don't show suffixes for to-scalar-int conversion insnsJan Beulich1-0/+6
2018-03-28Enhance the AARCH64 assembler to support LDFF1xx instructions which use REG+R...Nick Clifton1-0/+12
2018-03-22x86: drop pointless VecESizeJan Beulich1-0/+6
2018-03-22x86: drop remaining redundant DispNJan Beulich1-0/+6
2018-03-22x86: fix swapped operand handling for BNDMOVJan Beulich1-0/+8
2018-03-22x86/Intel: fix fallout from earlier template foldingJan Beulich1-0/+7
2018-03-22x86: fold a few XOP templatesJan Beulich1-0/+6
2018-03-14RISC-V: Add .insn support.Jim Wilson1-0/+4
2018-03-13Updated Russian and Brazilian Portuguese translations.Nick Clifton1-0/+4
2018-03-08x86-64: Also optimize "clr reg64"H.J. Lu1-0/+5
2018-03-08x86: Remove support for old (<= 2.8.1) versions of gccH.J. Lu1-0/+9
2018-03-08x86: fold several AVX512VL templatesJan Beulich1-0/+6
2018-03-08x86: fold certain AVX512 rotate and shift templatesJan Beulich1-0/+7
2018-03-08x86: fold VEX-encoded GFNI templatesJan Beulich1-0/+6
2018-03-08x86: fold a few AVX512F templatesJan Beulich1-0/+7
2018-03-08x86: fold LWP templatesJan Beulich1-0/+6
2018-03-08x86: fold FMA and FMA4 templatesJan Beulich1-0/+6
2018-03-08x86: drop {X,Y,Z}MMWORD_MNEM_SUFFIXJan Beulich1-0/+5
2018-03-08x86: drop bogus NoAVXJan Beulich1-0/+6
2018-03-08x86: avoid SSE check for LDMXCSR/STMXCSRJan Beulich1-0/+5
2018-03-08x86: drop FloatDJan Beulich1-0/+9
2018-03-08x86/Intel: correct disassembly of fsub*/fdiv*Jan Beulich1-0/+4
2018-03-08x86: bogus VMOVD with 64-bit operands should only allow for registersJan Beulich1-0/+5
2018-03-08x86: fold AVX vcvtpd2ps memory formsJan Beulich1-0/+6
2018-03-07XCOFF disassemblerAlan Modra1-0/+9
2018-03-03opcodes error messagesAlan Modra1-0/+31
2018-03-01x86: Encode AVX256/AVX512 vpsub[bwdq] with VEX128/EVEX128H.J. Lu1-0/+6
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