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AgeCommit message (Expand)AuthorFilesLines
2017-11-21[ARC] Improve printing of pc-relative instructions.claziss1-0/+5
2017-11-16Add new AArch64 FP16 FM{A|S} instructions.Tamar Christina1-0/+5
2017-11-16Add assembler and disassembler support for the new Armv8.4-a instructions for...Tamar Christina1-0/+10
2017-11-16x86: ignore high register select bit(s) in 32- and 16-bit modesJan Beulich1-0/+11
2017-11-15x86: use correct register namesJan Beulich1-0/+5
2017-11-15x86: drop VEXI4_Fixup()Jan Beulich1-0/+8
2017-11-15x86-64: don't allow use of %axl as accumulatorJan Beulich1-0/+5
2017-11-14x86: add disassembler support for XOP VPCOM* pseudo-opsJan Beulich1-0/+5
2017-11-14x86: add support for AVX-512 VPCMP*{B,W} pseudo-opsJan Beulich1-0/+13
2017-11-14x86: string insns don't allow displacementsJan Beulich1-0/+6
2017-11-13x86: {f,}xsave64 / {f,}xrstor64 / xsaveopt64 should not allow q suffixJan Beulich1-0/+6
2017-11-09Add assembler and disassembler support for the new Armv8.4-a registers for AA...Tamar Christina1-0/+17
2017-11-09Add the operand encoding types for the new Armv8.2-a back-ported instructions...Tamar Christina1-0/+7
2017-11-09Adds the new Fields and Operand types for the new instructions in Armv8.4-a.Tamar Christina1-0/+21
2017-11-09Split the ARM Crypto ISA extensions for AES and SHA1+2 into their own options...Tamar Christina1-0/+10
2017-11-08Split the AArch64 Crypto instructions for AES and SHA1+2 into their own optio...Nick Clifton1-0/+11
2017-11-08Adds command line support for Armv8.4-A, via the new command line option -mar...Jiong Wang1-0/+6
2017-11-07opcodes/arc: Fix incorrect insn_class for some nps insnsAndrew Burgess1-0/+4
2017-11-07ngettext supportAlan Modra1-0/+8
2017-11-03[ARC] Force the disassam to use the hexadecimal number for printingclaziss1-0/+8
2017-11-03[ARC] Sync opcode data base.claziss1-0/+25
2017-10-25PR22348, conflicting global vars in crx and cr16Alan Modra1-0/+13
2017-10-24RISC-V: Fix disassembly of c.addi4spn, c.addi16sp, c.lui when imm=0Andrew Waterman1-0/+10
2017-10-23Add missing ChangeLog entriesIgor Tsimbalist1-0/+110
2017-10-23Fix the master due to bad regenerated filesIgor Tsimbalist1-0/+5
2017-10-18[Visium] Disassemble the operands of the stop instruction.Eric Botcazou1-0/+4
2017-10-12FT32: support for FT32B processor - part 1James Bowman1-0/+6
2017-10-09S/390: Sync with latest POP - 3 new instructionsAndreas Krebbel1-0/+4
2017-10-09S/390: Sync with IBM z14 POP - SI_RD formatAndreas Krebbel1-0/+7
2017-10-01Add new mnemonics for VLE multiple load instructionsAlexander Fedotov1-0/+8
2017-09-27Add support for the new names of the RISC-V fmv.x.s and fmv.s.x instructions,...Nick Clifton1-0/+6
2017-09-26Allow the macw and macl instructions to be used on CPUs that have emacs support.Nick Clifton1-0/+6
2017-09-25Initialize 'imm' on opcodes/aarch64-opc.c:expand_fp_imm (and fix breakage on ...Sergio Durigan Junior1-0/+4
2017-09-11nds32: Rename __BIT() to N32_BIT().Kuan-Lin Chen1-0/+6
2017-09-09x86: Remove restriction on NOTRACK prefix positionH.J. Lu1-0/+6
2017-08-31Add updated French translations for opcodes and gprofNick Clifton1-0/+4
2017-08-30FT32: improve disassembly readabilityJames Bowman1-0/+5
2017-08-24[PowerPC VLE] Add SPE2 and EFS2 instructions supportAlexander Fedotov1-0/+60
2017-08-23ppc-opc.c formattingAlan Modra1-0/+7
2017-08-22RISC-V: Mark "c.nop" as an aliasPalmer Dabbelt1-0/+4
2017-08-21[PowerPC VLE] Add LSP (Lightweight Signal Processing) instruction supportAlexander Fedotov1-0/+34
2017-08-09[ARM] Don't warn on REG_SP when used in CRC32 instructionsJiong Wang1-0/+7
2017-08-07Mark big and mach with ATTRIBUTE_UNUSEDH.J. Lu1-0/+5
2017-08-07GDB/opcodes: Remove arch/mach/endian disassembler assertionsMaciej W. Rozycki1-0/+5
2017-07-25Fix typos in error and option messages in OPCODES library.Nick Clifton1-0/+39
2017-07-24[AArch64] Fix the bit pattern order in the comments in auto-generated fileJiong Wang1-0/+7
2017-07-21S/390: Support z14 as CPU name.Andreas Krebbel1-0/+5
2017-07-20Update the German translation for the opcodes library.Nick Clifton1-0/+4
2017-07-19[ARC] Add SecureShield AUX registersclaziss1-0/+12
2017-07-19[ARC] Add SJLI instruction.Claudiu Zissulescu1-0/+7
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