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AgeCommit message (Expand)AuthorFilesLines
2017-04-05-Wwrite-strings: Constify struct disassemble_info's disassembler_options fieldPedro Alves1-0/+7
2017-04-04RISC-V: Resurrect GP-relative disassembly hintsPalmer Dabbelt1-0/+5
2017-03-30Add support for the WebAssembly file format and the wasm32 ELF conversion to ...Pip Cet1-0/+6
2017-03-29opcodes: sparc: support missing SPARC ASIs from UA2005, UA2007, OSA2011, & OS...Jose E. Marchesi1-0/+6
2017-03-29PowerPC -Mraw disassemblyAlan Modra1-0/+9
2017-03-27PR21303, objdump doesn't show e200z4 insnsAlan Modra1-0/+6
2017-03-27Implement ARC NPS-400 Ultra Ip and Miscellaneous instructions.Rinat Zelig1-0/+10
2017-03-21S/390: Remove vx2 facility flagAndreas Krebbel1-0/+5
2017-03-21arc/nps400: Add cp16/cp32 instructions to opcodes libraryRinat Zelig1-0/+9
2017-03-17E6500 spr mnemonicsAlan Modra1-0/+7
2017-03-15RISC-V: Fix assembler for c.li, c.andi and c.addiwKito Cheng1-0/+6
2017-03-15RISC-V: Fix assembler for c.addi, rd can be x0Kito Cheng1-0/+4
2017-03-14RISC-V: Fix [dis]assembly of srai/srliAndrew Waterman1-0/+7
2017-03-09X86: Add pseudo prefixes to control encodingH.J. Lu1-0/+10
2017-03-09Use CpuCET on rdsspqH.J. Lu1-0/+5
2017-03-08Update -maltivec and -mvsx options to only enable their oldest instructions.Peter Bergner1-0/+5
2017-03-08Add support for the new 'lnia' extended mnemonic.Peter Bergner1-0/+4
2017-03-06Add support for Intel CET instructionsH.J. Lu1-0/+34
2017-03-06Don't decode powerpc insns with invalid fieldsAlan Modra1-0/+10
2017-02-28GDB: Add support for the new set/show disassembler-options commands.Peter Bergner1-0/+43
2017-02-28x86: fix handling of 64-bit operand size VPCMPESTR{I,M}Jan Beulich1-0/+12
2017-02-24[AArch64] Additional SVE instructionsRichard Sandiford1-0/+48
2017-02-24[AArch64] Add a "compnum" featureRichard Sandiford1-0/+9
2017-02-24x86: also correctly support TEST opcode aliasesJan Beulich1-0/+4
2017-02-23opcodes,gas: associate SPARC ASIs with an architecture level.Sheldon Lobo1-0/+7
2017-02-23x86: drop stray VEX opcode 82 referencesJan Beulich1-0/+5
2017-02-22aarch64: actually copy first operand in convert_bfc_to_bfm()Jan Beulich1-0/+5
2017-02-15Add SFENCE.VMA instructionAndrew Waterman1-0/+5
2017-02-15[AArch64] Add SVE system registersRichard Sandiford1-0/+5
2017-02-15[ARC] Fix assembler relaxation.Claudiu Zissulescu1-0/+16
2017-02-15Distinguish some of the registers different on ARC700 and HS38 cpusVineet Gupta1-0/+5
2017-02-14PowerPC register expression checksAlan Modra1-0/+6
2017-02-11Fix use after free in cgen instruction lookupAlan Modra1-0/+7
2017-02-10POWER9 add scv/rfscv instruction supportNicholas Piggin1-0/+4
2017-02-03Fix compile time warning messages when compiling binutils with gcc 7.0.1.Nick Clifton1-0/+8
2017-01-27Fix disassembling of TIC6X parallel instructions where the previous fetch pac...Alexis Deruell1-0/+7
2017-01-25Clarify that include/opcode/ files are part of GNU opcodesDimitar Dimitrov1-0/+4
2017-01-20Updated Irish translation for the opcodes library.Nick Clifton1-0/+4
2017-01-18[ARM] Fix the decoding of indexed element VCMLA instructionSzabolcs Nagy1-0/+4
2017-01-13Return -1 on memory error in print_insn_m68kYao Qi1-0/+7
2017-01-13Remove magic numbers in m68k-dis.c:print_insn_argYao Qi1-0/+16
2017-01-12Enable Intel AVX512_VPOPCNTDQ instructionsIgor Tsimbalist1-0/+13
2017-01-12Return -1 on memory error in print_insn_msp430Yao Qi1-0/+10
2017-01-05Prevent an abort in the FRV disassembler if the target bfd name is unknown.Nick Clifton1-0/+8
2017-01-04[AArch64] Add separate feature flag for weaker release consistent load insnsSzabolcs Nagy1-0/+5
2017-01-03Add support for the Q extension to the RISCV ISA.Kito Cheng1-0/+6
2017-01-03Add fall through comment.Dilyan Palauzov1-0/+4
2017-01-03Add new Serbian translation for the opcodes library.Nick Clifton1-0/+6
2017-01-02Regen opcodes cgen filesAlan Modra1-0/+29
2017-01-02Update year range in copyright notice of all files.Alan Modra1-0/+4
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