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AgeCommit message (Expand)AuthorFilesLines
2018-07-02GDB PR tdep/8282: MIPS: Wire in `set disassembler-options'Maciej W. Rozycki1-0/+13
2018-07-02[ARM] Update bfd's Tag_CPU_arch knowledgeThomas Preud'homme1-0/+8
2018-06-29Fix AArch64 encodings for by element instructions.Tamar Christina1-0/+14
2018-06-26Updated translations.Nick Clifton1-0/+6
2018-06-26Fix spelling mistakes.Nick Clifton1-0/+4
2018-06-24Regenerate configure and pot files with updated binutils version number.Nick Clifton1-0/+5
2018-06-24Add 2.30 branch notes to ChangeLogs and NEWS files.Nick Clifton1-0/+4
2018-06-22Correct negs aliasing on AArch64.Tamar Christina1-0/+6
2018-06-21MIPS/opcodes: Fix a typo in `-M ginv' option descriptionMaciej W. Rozycki1-0/+5
2018-06-20RISC-V: Accept constant operands in la and llaSebastian Huber1-0/+6
2018-06-19Bump to autoconf 2.69 and automake 1.15.1Simon Marchi1-0/+8
2018-06-14MIPS: Add Global INValidate ASE supportFaraz Shahbazker1-0/+10
2018-06-13MIPS: Add CRC ASE supportScott Egerton1-0/+9
2018-06-08Prevent undefined FMOV instructions being accepted by the AArch64 assembler.Egeyar Bagcioglu1-0/+6
2018-06-06Fix xtensa "clobbered by longjmp" warningsAlan Modra1-0/+5
2018-06-04xtensa: use property tables for correct disassemblyMax Filippov1-0/+12
2018-06-01Bump version number to 2.30.52H.J. Lu1-0/+4
2018-06-01x86: fold MOV to/from segment register templatesJan Beulich1-0/+5
2018-06-01x86: don't emit REX.W for SLDT and STRJan Beulich1-0/+5
2018-06-01x86/Intel: accept "oword ptr" for INVPCIDJan Beulich1-0/+5
2018-06-01Make _bfd_error_handler available outside libbfdAlan Modra1-0/+8
2018-05-30Add znver2 support.Amit Pawar1-0/+5
2018-05-25s12z regenAlan Modra1-0/+5
2018-05-21Remove fake operand handling for extended mnemonics.Peter Bergner1-0/+14
2018-05-18Add support for the Freescale s12z processor.John Darrington1-0/+11
2018-05-18opcodes sources should not include libbfd.hAlan Modra1-0/+6
2018-05-17Updated simplified Chinese translation for the opcodes directory.Nick Clifton1-0/+4
2018-05-16Fix disassembly mask for vector sdot on AArch64.Tamar Christina1-0/+6
2018-05-15Implement Read/Write constraints on system registers on AArch64Tamar Christina1-0/+28
2018-05-15Allow non-fatal errors to be emitted and for disassembly notes be placed on A...Tamar Christina1-0/+9
2018-05-15Modify AArch64 Assembly and disassembly functions to be able to fail and repo...Tamar Christina1-0/+66
2018-05-15Fix error messages in the NFP sources when building for 32-bit targets.Francois H. Theron1-0/+4
2018-05-09x86: Remove Disp<N> from movidir{i,64b}H.J. Lu1-0/+4
2018-05-09PR22069, Several instances of register accidentally spelled as regsiterAlan Modra1-0/+5
2018-05-08RISC-V: Add missing hint instructions from RV128I.Jim Wilson1-0/+9
2018-05-08Correct powerpc spe opcode lookupAlan Modra1-0/+6
2018-05-07Simplify VLE handling in print_insn_powerpc().Peter Bergner1-0/+6
2018-05-07Enable Intel MOVDIRI, MOVDIR64B instructionsH.J. Lu1-0/+18
2018-05-07x86: Replace AddrPrefixOp0 with AddrPrefixOpRegH.J. Lu1-0/+9
2018-05-07Cleanup ppc code dealing with opcode dumps.Peter Bergner1-0/+11
2018-05-01Fix unintialized memory in aarch64 opcodes.Tamar Christina1-0/+4
2018-04-30This patch adds support to objdump for disassembly of NFP (Netronome Flow Pro...Francois H. Theron1-0/+11
2018-04-27Revert "Enable Intel MOVDIRI, MOVDIR64B instructions."Igor Tsimbalist1-18/+0
2018-04-26Enable Intel MOVDIRI, MOVDIR64B instructions.Igor Tsimbalist1-0/+18
2018-04-26x86: fold various non-memory operand AVX512VL templatesJan Beulich1-0/+6
2018-04-26x86: CpuXSAVE is a prereq for various other featuresJan Beulich1-0/+8
2018-04-26x86: drop CpuRegMMX, CpuReg[XYZ]MM, and CpuRegMaskJan Beulich1-0/+16
2018-04-26x86: x87-related adjustmentsJan Beulich1-0/+6
2018-04-26x86: drop VexImmExtJan Beulich1-0/+7
2018-04-25x86: drop redundant AVX512VL shift templatesJan Beulich1-0/+6
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