Age | Commit message (Expand) | Author | Files | Lines |
2020-06-08 | x86: restrict use of register aliases | Jan Beulich | 1 | -0/+4 |
2020-06-06 | Power10 tidies | Alan Modra | 1 | -0/+4 |
2020-06-05 | bpf stack smashing detected | Alan Modra | 1 | -0/+5 |
2020-06-04 | cpu,gas,opcodes: remove no longer needed workaround from the BPF port | Jose E. Marchesi | 1 | -0/+8 |
2020-06-04 | opcodes: discriminate endianness and insn-endianness in CGEN ports | Jose E. Marchesi | 1 | -0/+43 |
2020-06-04 | opcodes: support insn endianness in cgen_cpu_open | Jose E. Marchesi | 1 | -0/+33 |
2020-06-03 | Updated Serbian translation for the opcodes sub-directory | Nick Clifton | 1 | -0/+4 |
2020-06-03 | RISC-V: Fix the error when building RISC-V linux native gdbserver. | Nelson Chu | 1 | -0/+5 |
2020-06-01 | Regen opcodes/bpf-desc.c | Alan Modra | 1 | -0/+4 |
2020-05-28 | cpu,opcodes: add instruction semantics to bpf.cpu and minor fixes | Jose E. Marchesi | 1 | -0/+8 |
2020-05-28 | ubsan: nios2: undefined shift | Alan Modra | 1 | -0/+5 |
2020-05-28 | asan: ns32k: use of uninitialized value | Alan Modra | 1 | -0/+6 |
2020-05-28 | Fix a potential use of an uninitialised value in the ns32k disassembler. | Nick Clifton | 1 | -0/+5 |
2020-05-26 | Fix extraction of signed constants in nios2 disassembler (again). | Sandra Loosemore | 1 | -0/+7 |
2020-05-26 | ChangeLog entries for f687f5f563 | Stefan Schulze Frielinghaus | 1 | -0/+6 |
2020-05-21 | Replace "if (x) free (x)" with "free (x)", opcodes | Alan Modra | 1 | -0/+22 |
2020-05-20 | [PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions... | Nelson Chu | 1 | -0/+31 |
2020-05-19 | Power10 dcbf, sync, and wait extensions. | Peter Bergner | 1 | -0/+17 |
2020-05-19 | or1k: Regenerate opcodes after removing 32-bit support | Stafford Horne | 1 | -0/+12 |
2020-05-11 | Power10 VSX scalar min-max-compare quad precision operations | Alan Modra | 1 | -0/+5 |
2020-05-11 | Power10 VSX load/store rightmost element operations | Alan Modra | 1 | -0/+5 |
2020-05-11 | Power10 test lsb by byte operation | Alan Modra | 1 | -0/+4 |
2020-05-11 | Power10 string operations | Alan Modra | 1 | -0/+5 |
2020-05-11 | Power10 Set boolean extension | Peter Bergner | 1 | -0/+5 |
2020-05-11 | Power10 bit manipulation operations | Alan Modra | 1 | -0/+7 |
2020-05-11 | Power10 VSX PCV generate operations | Alan Modra | 1 | -0/+5 |
2020-05-11 | Power10 VSX Mask Manipulation Operations | Alan Modra | 1 | -0/+9 |
2020-05-11 | Power10 Reduced precision outer product operations | Alan Modra | 1 | -0/+25 |
2020-05-11 | Power10 SIMD permute class operations | Alan Modra | 1 | -0/+15 |
2020-05-11 | Power10 128-bit binary integer operations | Alan Modra | 1 | -0/+8 |
2020-05-11 | Power10 VSX 32-byte storage access | Alan Modra | 1 | -0/+7 |
2020-05-11 | Power10 vector integer multiply, divide, modulo insns | Alan Modra | 1 | -0/+6 |
2020-05-11 | Power10 byte reverse instructions | Peter Bergner | 1 | -0/+4 |
2020-05-11 | Power10 Copy/Paste Extensions | Peter Bergner | 1 | -0/+6 |
2020-05-11 | Power10 Add new L operand to the slbiag instruction | Peter Bergner | 1 | -0/+4 |
2020-05-11 | PowerPC Default disassembler to -Mpower10 | Alan Modra | 1 | -0/+4 |
2020-05-11 | PowerPC Rename powerxx to power10 | Alan Modra | 1 | -0/+6 |
2020-05-11 | Updated French translation for the ld sub-directory and an update Spanish tra... | Nick Clifton | 1 | -0/+4 |
2020-04-30 | AArch64: add GAS support for UDF instruction | Alex Coplan | 1 | -0/+12 |
2020-04-29 | Also use unsigned 8-bit immediate values for the LDRC and SETRC insns. | Nick Clifton | 1 | -0/+6 |
2020-04-29 | Updated Serbian translation for the binutils sub-directory, and Swedish trans... | Nick Clifton | 1 | -0/+4 |
2020-04-29 | Fix the disassmbly of SH instructions which have an unsigned 8-bit immediate ... | Nick Clifton | 1 | -0/+8 |
2020-04-21 | Disallow PC relative for CMPI on MC68000/10 | Andreas Schwab | 1 | -0/+6 |
2020-04-20 | [AArch64, Binutils] Add missing TSB instruction | Sudakshina Das | 1 | -0/+15 |
2020-04-20 | [AArch64, Binutils] Make hint space instructions valid for Armv8-a | Sudakshina Das | 1 | -0/+12 |
2020-04-17 | [PATCH v2] binutils: arm: Fix disassembly of conditional VDUPs. | Fredrik Strupe | 1 | -0/+6 |
2020-04-16 | cpu,gas,opcodes: support for eBPF JMP32 instruction class | David Faust | 1 | -0/+7 |
2020-04-07 | Add support for intel TSXLDTRK instructions$ | Cui,Lili | 1 | -0/+14 |
2020-04-02 | Add support for intel SERIALIZE instruction | LiliCui | 1 | -0/+12 |
2020-03-26 | Re: H8300 use of uninitialised value | Alan Modra | 1 | -0/+13 |