aboutsummaryrefslogtreecommitdiff
path: root/ld
AgeCommit message (Collapse)AuthorFilesLines
2016-06-22Add PT_GNU_SHR/SHF_GNU_SHARABLE/SHN_GNU_SHARABLE_COMMON support to gas/ldusers/hjl/sharableH.J. Lu7-0/+47
PT_GNU_SHR/SHF_GNU_SHARABLE/SHN_GNU_SHARABLE_COMMON are used to group data into a PT_GNU_SHR to improve performance on NUMA system.
2016-06-22ld: Add a linker configure option --enable-relroH.J. Lu9-4/+112
Add a configure option --enable-relro to decide whether -z relro should be enabled in ELF linker by default. Default to yes for all Linux targets, except FRV, HPPA, IA64 and MIPS, since many relro tests fail on these targets. PR ld/20283 * NEWS: Mention --enable-relro. * configure.ac: Add --enable-relro. (DEFAULT_LD_Z_RELRO): New. Set by --enable-relro. * configure.tgt (ac_default_ld_z_relro): Default it to 1 for some Linux targets. * config.in: Regenerated. * configure: Likewise. * emultempl/elf32.em (gld${EMULATION_NAME}_before_parse): Set link_info.relro to DEFAULT_LD_Z_RELRO. * testsuite/config/default.exp (ld_elf_shared_opt): New. * testsuite/lib/ld-lib.exp (run_dump_test): Pass $ld_elf_shared_opt to ld for ELF targets with shared object support. (run_ld_link_tests): Likewise.
2016-06-21MIPS/BFD: Don't stop processing on a cross-mode jump conversion errorMaciej W. Rozycki3-1/+14
As with commit ed53407eec9e ("MIPS/BFD: Don't stop processing on `bfd_reloc_outofrange'") don't bail out right away and instead continue processing on a cross-mode jump conversion error, so that any further issues are also reported. Adjust message formatting accordingly, using `%X' to abort processing at conclusion. Remove the full stop from the end of the message, for consistency across error reporting. Adjust the corresponding test case accordingly and make it trigger the error twice. bfd/ * elfxx-mips.c (mips_elf_perform_relocation): Call `info->callbacks->einfo' rather than `*_bfd_error_handler' and use the `%X%H' format for the cross-mode jump conversion error message. Remove the full stop from the end of the message. Continue processing rather than returning failure. ld/ * testsuite/ld-mips-elf/mode-change-error-1a.s: Trigger an error twice rather than once. * testsuite/ld-mips-elf/mode-change-error-1.d: Adjust accordingly. Remove the full stop from the end of the message.
2016-06-21Arc assembler: Convert nps400 from a machine type to an extension.Graham Markall3-2/+7
gas * config/tc-arc.c (check_cpu_feature, md_parse_option): Add nps400 option and feature. Add check for nps400 feature. Refactor existing checks to check subclass before feature enablement. (md_show_usage): Document flags for NPS-400 and add some other undocumented flags. (cpu_type): Remove nps400 CPU type entry (check_zol): Remove bfd_mach_arc_nps400 case. (md_show_usage): Add help on -mcpu=nps400. (cpu_types): Add entry for nps400 as arc700 plus nps400 extension set. * doc/c-arc.texi: Document the -mnps400, -mspfp, -mdpfp, and -fpuda flags. Document -mcpu=nps400. * testsuite/gas/arc/nps-400-0.d: Use -mcpu=arc700 -mnps400. Change expected flags to match ARC700 instead of NPS400. * testsuite/gas/arc/nps-400-1.d: Use -mcpu=arc700 -mnps400. * testsuite/gas/arc/nps-400-2.d: Likewise. * testsuite/gas/arc/nps-400-3.d: Likewise. * testsuite/gas/arc/nps-400-4.d: Likewise. * testsuite/gas/arc/nps-400-5.d: Likewise. * testsuite/gas/arc/nps-400-6.d: Likewise. * testsuite/gas/arc/nps-400-7.d: Likewise. * testsuite/gas/arc/textinsn2op01.s: Change opcode of myinsn to avoid clash with cbba instruction. * testsuite/gas/arc/textinsn2op01.d: Likewise. * testsuite/gas/arc/textinsn3op.d: Likewise. * testsuite/gas/arc/textinsn3op.s: Likewise. * testsuite/gas/arc/nps-400-0.d: Test using NPS-400 using -mcpu=nps400 as an alternative to -mcpu=arc700 -mnps400 flags. binutils* readelf.c (decode_ARC_machine_flags): Remove E_ARC_MACH_NPS400 case. ld * testsuite/ld-arc/nps-1a.d: Use -mcpu=arc700 -mnps400. * testsuite/ld-arc/nps-1b.d: Likewise. include * opcode/arc.h: Add nps400 extension and instruction subclass. Remove ARC_OPCODE_NPS400 * elf/arc.h: Remove E_ARC_MACH_NPS400 opcodes * arc-dis.c (arc_insn_length): Add comment on instruction length. Use same method for determining instruction length on ARC700 and NPS-400. (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400. * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions with the NPS400 subclass. * arc-opc.c: Likewise. bfd * archures.c: Remove bfd_mach_arc_nps400. * bfd-in2.h: Likewise. * cpu-arc.c (arch_info_struct): Likewise. * elf32-arc.c (arc_elf_object_p, arc_elf_final_write_processing): Likewise.
2016-06-20Use the IR symbol table for the IR input objectH.J. Lu4-0/+37
ELF linker shouldn't skip the IR object when searching the symbol table of an archive element. If linker doesn't know if the object file is an IR object, it should give LTO plugin a chance to get the correct symbol table and use the IR symbol table if the input is an IR object. bfd/ PR ld/18250 PR ld/20267 * elflink.c: Include plugin.h if BFD_SUPPORTS_PLUGINS is defined. (elf_link_is_defined_archive_symbol): Call bfd_link_plugin_object_p on unknown plugin object and use the IR symbol table if the input is an IR object. * plugin.c (bfd_link_plugin_object_p): New function. * plugin.h (bfd_link_plugin_object_p): New prototype. ld/ PR ld/20267 * testsuite/ld-plugin/lto.exp (lto_link_tests): Add test for PR ld/20267. (lto_run_tests): Likewise. * testsuite/ld-plugin/pr20267a.c: New file. * testsuite/ld-plugin/pr20267b.c: Likewise.
2016-06-20PR ld/20276: Set non_ir_ref on common symbolAlan Modra6-13/+58
Also, don't check alignment on symbol from plugin dummy input. bfd/ PR ld/20276 * elflink.c (elf_link_add_object_symbols): Don't check alignment on symbol from plugin dummy input. ld/ PR ld/20276 * plugin.c (plugin_notice): Set non_ir_ref on common symbols. * testsuite/ld-plugin/lto.exp (lto_link_tests): Add test for PR ld/20276. (lto_run_tests): Likewise. * testsuite/ld-plugin/pass.out: New file. * testsuite/ld-plugin/pr20276a.c: Likewise. * testsuite/ld-plugin/pr20276b.c: Likewise.
2016-06-18Rename bfd_plugin_uknown to bfd_plugin_unknownH.J. Lu2-1/+6
bfd/ * bfd.c (bfd_plugin_format): Rename bfd_plugin_uknown to bfd_plugin_unknown. * bfd-in2.h: Regenerated. * plugin.c (bfd_plugin_object_p): Replace bfd_plugin_uknown with bfd_plugin_unknown. ld/ * plugin.c (plugin_object_p): Replace bfd_plugin_uknown with bfd_plugin_unknown.
2016-06-18Don't generate PLT for IFUNC GOT/pointer referenceH.J. Lu83-115/+1342
If a backend supports it, PLT entry isn't needed when all references to a STT_GNU_IFUNC symbols are done via GOT or static function pointers. For GOT entries, We generate dynamic R_*_GLOB_DAT relocations for preemptable symbols and R_*_IRELATIVE relocations for non-preemptable symbols to update them with real function address. For static pointer pointers, we generate dynamic pointer relocations and store them in: 1. .rel[a].ifunc section in PIC object. 2. .rel[a].got section in dynamic executable. 3. .rel[a].iplt section in static executable. We don't allocate GOT entry if it isn't used. bfd/ PR ld/20253 * elf-bfd.h (_bfd_elf_allocate_ifunc_dyn_relocs): Add an bfd_boolean argument. * elf-ifunc.c (_bfd_elf_create_ifunc_sections): Replace "shared object" with "PIC object" in comments. (_bfd_elf_allocate_ifunc_dyn_relocs): Updated. Replace "shared object" with "PIC object" in comments. Avoid PLT if requested. Generate dynamic relocations for non-GOT references. Make room for the special first entry in PLT and allocate PLT entry only for PLT and PC-relative references. Store dynamic GOT relocations in .rel[a].iplt section for static executables. If PLT isn't used, always use GOT for symbol value. Don't allocate GOT entry if it isn't used. * elf32-i386.c (elf_i386_check_relocs): Increment PLT reference count only in the code section. Allocate dynamic pointer relocation against STT_GNU_IFUNC symbol in the non-code section. (elf_i386_adjust_dynamic_symbol): Increment PLT reference count only for PC-relative references. (elf_i386_allocate_dynrelocs): Pass TRUE to _bfd_elf_allocate_ifunc_dyn_relocs. (elf_i386_relocate_section): Allow R_386_GOT32/R_386_GOT32X relocations against STT_GNU_IFUNC symbols without PLT. Generate dynamic pointer relocation against STT_GNU_IFUNC symbol in the non-code section and store it in the proper REL section. Don't allow non-pointer relocation against STT_GNU_IFUNC symbol without PLT. (elf_i386_finish_dynamic_symbol): Generate dynamic R_386_IRELATIVE and R_386_GLOB_DAT GOT relocations against STT_GNU_IFUNC symbols without PLT. (elf_i386_finish_dynamic_sections): Don't handle local STT_GNU_IFUNC symbols here. (elf_i386_output_arch_local_syms): Handle local STT_GNU_IFUNC symbols here. (elf_backend_output_arch_local_syms): New. * elf32-x86-64.c (elf_i386_check_relocs): Increment PLT reference count only in the code section. Allocate dynamic pointer relocation against STT_GNU_IFUNC symbol in the non-code section. (elf_x86_64_adjust_dynamic_symbol): Increment PLT reference count only for PC-relative references. (elf_x86_64_allocate_dynrelocs): Pass TRUE to _bfd_elf_allocate_ifunc_dyn_relocs. (elf_x86_64_relocate_section): Allow R_X86_64_GOTPCREL, R_X86_64_GOTPCRELX, R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCREL64 relocations against STT_GNU_IFUNC symbols without PLT. Generate dynamic pointer relocation against STT_GNU_IFUNC symbol in the non-code section and store it in the proper RELA section. Don't allow non-pointer relocation against STT_GNU_IFUNC symbol without PLT. (elf_x86_64_finish_dynamic_symbol): Generate dynamic R_X86_64_IRELATIVE and R_X86_64_GLOB_DAT GOT relocations against STT_GNU_IFUNC symbols without PLT. (elf_x86_64_finish_dynamic_sections): Don't handle local STT_GNU_IFUNC symbols here. (elf_x86_64_output_arch_local_syms): Handle local STT_GNU_IFUNC symbols here. (elf_backend_output_arch_local_syms): New. * elfnn-aarch64.c (elfNN_aarch64_allocate_ifunc_dynrelocs): Pass FALSE to _bfd_elf_allocate_ifunc_dyn_relocs. ld/ PR ld/20253 * testsuite/ld-i386/i386.exp: Run PR ld/20253 tests. * testsuite/ld-i386/no-plt.exp: Likewise. * testsuite/ld-x86-64/no-plt.exp: Likewise. * testsuite/ld-i386/pr13302.d: Remove .rel.plt section. * testsuite/ld-ifunc/ifunc-13-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-13-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-15-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-15-x86-64.d: Likewise. * testsuite/ld-x86-64/pr13082-5a.d: Likewise. * testsuite/ld-x86-64/pr13082-5b.d: Likewise. * testsuite/ld-x86-64/pr13082-6a.d: Likewise. * testsuite/ld-x86-64/pr13082-6b.d: Likewise. * testsuite/ld-i386/pr20244-2a.d: Remove .plt section. * testsuite/ld-ifunc/ifunc-21-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-21-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-22-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-22-x86-64.d: Likewise. * testsuite/ld-i386/pr20244-2b.d: Updated. * testsuite/ld-i386/pr20244-2c.d: Likewise. * testsuite/ld-ifunc/ifunc-18a-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-18a-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-18b-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-18b-x86-64.d: Likewise. * testsuite/ld-i386/pr20253-1a.c: New file. * testsuite/ld-i386/pr20253-1b.S: Likewise. * testsuite/ld-i386/pr20253-1c.S: Likewise. * testsuite/ld-i386/pr20253-1d.S: Likewise. * testsuite/ld-i386/pr20253-2a.c: Likewise. * testsuite/ld-i386/pr20253-2b.S: Likewise. * testsuite/ld-i386/pr20253-2c.S: Likewise. * testsuite/ld-i386/pr20253-2d.S: Likewise. * testsuite/ld-i386/pr20253-3.d: Likewise. * testsuite/ld-i386/pr20253-3.s: Likewise. * testsuite/ld-i386/pr20253-4.s: Likewise. * testsuite/ld-i386/pr20253-4a.d: Likewise. * testsuite/ld-i386/pr20253-4b.d: Likewise. * testsuite/ld-i386/pr20253-4c.d: Likewise. * testsuite/ld-i386/pr20253-5.d: Likewise. * testsuite/ld-i386/pr20253-5.s: Likewise. * testsuite/ld-ifunc/ifunc-23-x86.s: Likewise. * testsuite/ld-ifunc/ifunc-23a-x86.d: Likewise. * testsuite/ld-ifunc/ifunc-23b-x86.d: Likewise. * testsuite/ld-ifunc/ifunc-23c-x86.d: Likewise. * testsuite/ld-ifunc/ifunc-24-x86.s: Likewise. * testsuite/ld-ifunc/ifunc-24a-x86.d: Likewise. * testsuite/ld-ifunc/ifunc-24b-x86.d: Likewise. * testsuite/ld-ifunc/ifunc-24c-x86.d: Likewise. * testsuite/ld-ifunc/ifunc-25-x86.s: Likewise. * testsuite/ld-ifunc/ifunc-25a-x86.d: Likewise. * testsuite/ld-ifunc/ifunc-25b-x86.d: Likewise. * testsuite/ld-ifunc/ifunc-25c-x86.d: Likewise. * testsuite/ld-x86-64/pr20253-1.s: Likewise. * testsuite/ld-x86-64/pr20253-1a.d: Likewise. * testsuite/ld-x86-64/pr20253-1b.d: Likewise. * testsuite/ld-x86-64/pr20253-1c.d: Likewise. * testsuite/ld-x86-64/pr20253-1d.d: Likewise. * testsuite/ld-x86-64/pr20253-1e.d: Likewise. * testsuite/ld-x86-64/pr20253-1f.d: Likewise. * testsuite/ld-x86-64/pr20253-1g.d: Likewise. * testsuite/ld-x86-64/pr20253-1h.d: Likewise. * testsuite/ld-x86-64/pr20253-1i.d: Likewise. * testsuite/ld-x86-64/pr20253-1j.d: Likewise. * testsuite/ld-x86-64/pr20253-1k.d: Likewise. * testsuite/ld-x86-64/pr20253-1l.d: Likewise. * testsuite/ld-x86-64/pr20253-2a.c: Likewise. * testsuite/ld-x86-64/pr20253-2b.S: Likewise. * testsuite/ld-x86-64/pr20253-2c.S: Likewise. * testsuite/ld-x86-64/pr20253-2d.S: Likewise. * testsuite/ld-x86-64/pr20253-3.d: Likewise. * testsuite/ld-x86-64/pr20253-3.s: Likewise. * testsuite/ld-x86-64/pr20253-4.s: Likewise. * testsuite/ld-x86-64/pr20253-4a.d: Likewise. * testsuite/ld-x86-64/pr20253-4b.d: Likewise. * testsuite/ld-x86-64/pr20253-4c.d: Likewise. * testsuite/ld-x86-64/pr20253-4d.d: Likewise. * testsuite/ld-x86-64/pr20253-4e.d: Likewise. * testsuite/ld-x86-64/pr20253-4f.d: Likewise. * testsuite/ld-x86-64/pr20253-5.s: Likewise. * testsuite/ld-x86-64/pr20253-5a.d: Likewise. * testsuite/ld-x86-64/pr20253-5b.d: Likewise. * testsuite/ld-ifunc/ifunc-18a-i386.d: Remove extra IRELATIVE relocation. * testsuite/ld-ifunc/ifunc-18a-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-18b-i386.d: Likewise. * testsuite/ld-ifunc/ifunc-18b-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-18a.s: Fix a typo. * testsuite/ld-x86-64/x86-64.exp: Run pr20253-1 tests.
2016-06-17Add support for Thumb-2 long branch veneersThomas Preud'homme5-13/+34
2016-06-17 Thomas Preud'homme <thomas.preudhomme@arm.com> Tony Wang <tony.wang@arm.com> bfd/ * elf32-arm.c (elf32_arm_stub_long_branch_thumb2_only): Define stub sequence. (stub_long_branch_thumb2_only): Define stub. (arm_stub_is_thumb): Add case for arm_stub_long_branch_thumb2_only. (arm_stub_long_branch_thumb2_only): Likewise. (arm_type_of_stub): Use arm_stub_long_branch_thumb2_only for Thumb-2 capable targets. ld/ * testsuite/ld-arm/arm-elf.exp (Thumb-Thumb farcall M profile): Assemble for ARMv6-M. (Thumb2-Thumb2 farcall M profile): New testcase. * testsuite/ld-arm/farcall-thumb2-thumb2-m.d: New file. * testsuite/ld-arm/jump-reloc-veneers-cond-long-backward.d: Update to reflect the use of Thumb-2 veneers for Thumb-2 capable targets. * testsuite/ld-arm/jump-reloc-veneers-cond-long.d: Likewise.
2016-06-16Add missing ChangeLog entriesH.J. Lu1-0/+7
commit bf52d7c72035679e6b3ab601133c56a4388f4dc9 Author: H.J. Lu <hjl.tools@gmail.com> Date: Wed Jun 15 10:35:38 2016 -0700 Don't check undefined symbol for IFUNC reloc
2016-06-16Don't check undefined symbol for IFUNC relocH.J. Lu3-4/+23
Since x86 elf_*_check_relocs is called after all symbols have been resolved, there is no need to check undefined symbols for relocations against IFUNC symbols. bfd/ * elf32-i386.c (elf_i386_check_relocs): Don't check undefined symbols for relocations against IFUNC symbols. * elf64-x86-64.c (elf_x86_64_check_relocs): Likewise. ld/ * testsuite/ld-i386/i386.exp: Run pr19636-2e-nacl. * testsuite/ld-i386/pr19636-2e.d: Skip for NaCl targets. Remove .rel.plt section. * testsuite/ld-i386/pr19636-2e-nacl.d: New file.
2016-06-15X86: Add tests for static function pointerH.J. Lu24-6/+116
* testsuite/ld-i386/no-plt-check1a.S (check): Test static function pointer. * testsuite/ld-i386/no-plt-check1b.S (check): Likewise. * testsuite/ld-x86-64/no-plt-check1.S (check): Likewise. * testsuite/ld-i386/no-plt-extern1a.S (func_p): New. Static function pointer. * testsuite/ld-i386/no-plt-extern1b.S (func_p): Likewise. * testsuite/ld-x86-64/no-plt-extern1.S (func_p): Likewise. * testsuite/ld-i386/no-plt-1a.dd: Updated. * testsuite/ld-i386/no-plt-1b.dd: Likewise. * testsuite/ld-i386/no-plt-1c.dd: Likewise. * testsuite/ld-i386/no-plt-1d.dd: Likewise. * testsuite/ld-i386/no-plt-1e.dd: Likewise. * testsuite/ld-i386/no-plt-1f.dd: Likewise. * testsuite/ld-i386/no-plt-1g.dd: Likewise. * testsuite/ld-i386/no-plt-1h.dd: Likewise. * testsuite/ld-i386/no-plt-1i.dd: Likewise. * testsuite/ld-i386/no-plt-1j.dd: Likewise. * testsuite/ld-x86-64/no-plt-1a.dd: Likewise. * testsuite/ld-x86-64/no-plt-1b.dd: Likewise. * testsuite/ld-x86-64/no-plt-1c.dd: Likewise. * testsuite/ld-x86-64/no-plt-1d.dd: Likewise. * testsuite/ld-x86-64/no-plt-1e.dd: Likewise. * testsuite/ld-x86-64/no-plt-1f.dd: Likewise. * testsuite/ld-x86-64/no-plt-1g.dd: Likewise.
2016-06-15Fix PR ld/20254Senthil Kumar Selvaraj3-0/+29
This patch fixes another edge case related to alignment property records - reloc offsets adjacent to property record offsets were not getting adjusted during relaxation. bfd/ PR ld/20254 * elf32-avr.c (elf32_avr_relax_delete_bytes): Adjust reloc offsets until reloc_toaddr. ld/ PR ld/20254 * testsuite/ld-avr/avr-prop-6.d: New test. * testsuite/ld-avr/avr-prop-6.s: New test.
2016-06-14Formatting fixes.Alan Modra10-185/+207
* ldbuildid.c: Formatting. * ldcref.c: Formatting. * ldctor.c: Formatting. * ldemul.c: Formatting. * ldexp.c: Formatting. * ldfile.c: Formatting. * ldlang.c: Formatting. * ldmain.c: Formatting. * ldwrite.c: Formatting.
2016-06-14Delete bfd_my_archive macroAlan Modra5-16/+23
Many more places use abfd->my_archive rather than bfd_my_archive (abfd), so let's make the code consistently use the first idiom. bfd/ * bfd-in.h (bfd_my_archive): Delete. * bfd-in2.h: Regenerate. binutils/ * ar.c: Expand uses of bfd_my_archive. * size.c: Likewise. ld/ * ldlang.c: Expand uses of bfd_my_archive. * ldmain.c: Likewise. * ldmisc.c: Likewise. * plugin.c: Likewise.
2016-06-14Set my_archive for thin archivesAlan Modra4-7/+23
LTO plugin support in plugin_maybe_claim wants to close the IR bfd after replacing it with the recompiled object, but can't do so for archive elements due to various pointers that access the archive bfd. Thin archives have the same problem. They too cannot have their element bfds closed. PR ld/20241 bfd/ * archive.c (open_nested_file): Set my_archive. * bfd.c (_bfd_default_error_handler <%B>): Exclude archive file name for thin archives. * bfdio.c (bfd_tell): Don't adjust origin for thin archives. (bfd_seek): Likewise. * bfdwin.c (bfd_get_file_window): Likewise. * cache.c (cache_bmmap): Likewise. (bfd_cache_lookup_worker): Don't look in my_archive for thin archives. * mach-o.c (bfd_mach_o_follow_dsym): Don't open my_archive for thin archives. * plugin.c (try_claim): Likewise. * xcofflink.c (xcoff_link_add_dynamic_symbols): Use import path of file within thin archive, not the archive. binutils/ * bucomm.c (bfd_get_archive_filename): Return file name within thin archive. ld/ * ldmain.c (add_archive_element): Just print file name of file within thin archives. * ldmisc.c (vfinfo): Likewise. * plugin.c (plugin_object_p): Open file within thin archives. (plugin_maybe_claim): Expand comment.
2016-06-13Add the GOT base for GOT32 relocs against IFUNCH.J. Lu12-0/+235
Add the GOT base for R_386_GOT32/R_386_GOT32X relocations against IFUNC symbols if there is no base register and disallow them for PIC. bfd/ PR ld/20244 * elf32-i386.c (elf_i386_relocate_section): Add the .got.plt section address for R_386_GOT32/R_386_GOT32X relocations against IFUNC symbols if there is no base register and return error for PIC. ld/ PR ld/20244 * testsuite/ld-i386/i386.exp: Run pr20244-2a, pr20244-2b, pr20244-2c and pr20244-2d. * testsuite/ld-i386/no-plt.exp: Run pr20244-3a and pr20244-3b. * testsuite/ld-i386/pr20244-2.s: New file. * testsuite/ld-i386/pr20244-2a.d: Likewise. * testsuite/ld-i386/pr20244-2b.d: Likewise. * testsuite/ld-i386/pr20244-2c.d: Likewise. * testsuite/ld-i386/pr20244-2d.d: Likewise. * testsuite/ld-i386/pr20244-3a.c: Likewise. * testsuite/ld-i386/pr20244-3b.S: Likewise. * testsuite/ld-i386/pr20244-3c.S: Likewise. * testsuite/ld-i386/pr20244-3d.S: Likewise.
2016-06-13Add 2 i386 tests to call IFUNC functions via GOTH.J. Lu6-0/+196
bfd/ * elf32-i386.c (elf_i386_relocate_section): Simplify IFUNC GOT32 adjustment for static executables. ld/ 2016-06-13 H.J. Lu <hongjiu.lu@intel.com> * testsuite/ld-i386/i386.exp: Run ifunc-1a and ifunc-1b. * testsuite/ld-i386/ifunc-1a.c: New file. * testsuite/ld-i386/ifunc-1b.S: Likewise. * testsuite/ld-i386/ifunc-1c.S: Likewise. * testsuite/ld-i386/ifunc-1d.S: Likewise.
2016-06-13[ARC] XFAIL S-Records tests for both little and big endian ARC target.Cupertino Miranda2-2/+7
ld/ 2016-06-13 Cupertino Miranda <cmiranda@synospsy.com> * testsuite/ld-srec/srec.exp: Changed to XFAIL on both little and big endian ARC targets.
2016-06-12Update x86-64 no-PLT tests for x32H.J. Lu16-40/+58
X32 has different output formats for readelf and objdump as well as a different conversion of load symbol address via GOT. * testsuite/ld-x86-64/libno-plt-1b.dd: Updated for x32. * testsuite/ld-x86-64/libno-plt-1b.rd: Likewise. * testsuite/ld-x86-64/no-plt-1a.dd: Likewise. * testsuite/ld-x86-64/no-plt-1a.rd: Likewise. * testsuite/ld-x86-64/no-plt-1b.dd: Likewise. * testsuite/ld-x86-64/no-plt-1b.rd: Likewise. * testsuite/ld-x86-64/no-plt-1c.dd: Likewise. * testsuite/ld-x86-64/no-plt-1c.rd: Likewise. * testsuite/ld-x86-64/no-plt-1d.dd: Likewise. * testsuite/ld-x86-64/no-plt-1e.dd: Likewise. * testsuite/ld-x86-64/no-plt-1e.rd: Likewise. * testsuite/ld-x86-64/no-plt-1f.dd: Likewise. * testsuite/ld-x86-64/no-plt-1f.rd: Likewise. * testsuite/ld-x86-64/no-plt-1g.dd: Likewise. * testsuite/ld-x86-64/no-plt-1g.rd: Likewise.
2016-06-11Subtract GOT base only with a base registerH.J. Lu6-0/+70
When relocating R_386_GOT32 in "op $0, bar@GOT", we shouldn't subtract GOT base without a base register and we should disallow it without a base register for PIC. bfd/ PR ld/20244 * elf32-i386.c (elf_i386_relocate_section): When relocating R_386_GOT32, return error without a base register for PIC and subtract the .got.plt section address only with a base register. ld/ PR ld/20244 * testsuite/ld-i386/i386.exp: Run pr20244-1a and pr20244-1b. * testsuite/ld-i386/pr20244-1.s: New file. * testsuite/ld-i386/pr20244-1a.d: Likewise. * testsuite/ld-i386/pr20244-1b.d: Likewise. * testsuite/ld-i386/pr20244-1c.d: Likewise.
2016-06-09Add missing ChangeLog entriesH.J. Lu1-0/+32
2016-06-09Fix PR 20221 - adjust syms and relocs only if relax shrunk section.Denis Chertykov3-0/+24
This patch fixes an edge case in linker relaxation that causes symbol values to be computed incorrectly in the presence of align directives in input source code. bfd/ * elf32-avr.c (elf32_avr_relax_delete_bytes): Adjust syms and relocs only if shrinking occurred. ld/ * testsuite/ld-avr/avr-prop-5.d: New. * testsuite/ld-avr/avr-prop-5.s: New.
2016-06-09Print symbol names in comments for LDS/STS disassembly.Denis Chertykov5-0/+81
This patch adds default data address space origin (0x800000) to the symbol addresses. when disassemble lds/sts instructions. So that symbol names shall be printed in comments for lds/sts instructions disassemble. ld/ * testsuite/ld-avr/lds-mega.d: New test. * testsuite/ld-avr/lds-mega.s: New test source. * testsuite/ld-avr/lds-tiny.d: New test. * testsuite/ld-avr/lds-tiny.s: New test source. opcodes/ * avr-dis.c (avr_operand): Add default data address space origin (0x800000) to the address and set as symbol address for LDS/ STS immediate operands.
2016-06-08i386: Test external function reference without PLTH.J. Lu29-0/+876
To call an external function, the direct branch to the PLT entry can be replaced by an indirect branch via the GOT slot, which is similar to the first instruction in the PLT slot. Instead using the PLT slot as function address, the function address is retrieved from the GOT slot. The R_386_GOT32X relocation can be used to compute the address of the symbol’s GOT entry without base register when PIC is disabled. In non-PIC executable, call/jmp *func@GOT should be used for indirect branch via the GOT slot and movl func@GOT, %eax should be used to load function address. Unlike PIC case, no register is needed to access GOT. If linker determines the function is defined locally, it converts indirect branch via the GOT slot to direct branch with a nop prefix and converts load via the GOT slot to load immediate or lea. * testsuite/ld-i386/libno-plt-1b.dd: New file. * testsuite/ld-i386/libno-plt-1b.rd: Likewise. * testsuite/ld-i386/no-plt-1a.dd: Likewise. * testsuite/ld-i386/no-plt-1a.rd: Likewise. * testsuite/ld-i386/no-plt-1b.dd: Likewise. * testsuite/ld-i386/no-plt-1b.rd: Likewise. * testsuite/ld-i386/no-plt-1c.dd: Likewise. * testsuite/ld-i386/no-plt-1c.rd: Likewise. * testsuite/ld-i386/no-plt-1d.dd: Likewise. * testsuite/ld-i386/no-plt-1d.rd: Likewise. * testsuite/ld-i386/no-plt-1e.dd: Likewise. * testsuite/ld-i386/no-plt-1e.rd: Likewise. * testsuite/ld-i386/no-plt-1f.dd: Likewise. * testsuite/ld-i386/no-plt-1f.rd: Likewise. * testsuite/ld-i386/no-plt-1g.dd: Likewise. * testsuite/ld-i386/no-plt-1g.rd: Likewise. * testsuite/ld-i386/no-plt-1h.dd: Likewise. * testsuite/ld-i386/no-plt-1h.rd: Likewise. * testsuite/ld-i386/no-plt-1i.dd: Likewise. * testsuite/ld-i386/no-plt-1i.rd: Likewise. * testsuite/ld-i386/no-plt-1j.dd: Likewise. * testsuite/ld-i386/no-plt-1j.rd: Likewise. * testsuite/ld-i386/no-plt-check1a.S: Likewise. * testsuite/ld-i386/no-plt-check1b.S: Likewise. * testsuite/ld-i386/no-plt-extern1a.S: Likewise. * testsuite/ld-i386/no-plt-extern1b.S: Likewise. * testsuite/ld-i386/no-plt-func1.c: Likewise. * testsuite/ld-i386/no-plt-main1.c: Likewise. * testsuite/ld-i386/no-plt.exp: Likewise.
2016-06-08Update test nameH.J. Lu2-1/+6
* testsuite/ld-x86-64/tls.exp (run_cc_link_tests): Update test name.
2016-06-08Support i386 TLS code sequences without PLTH.J. Lu30-0/+2554
We can generate i386 TLS code sequences for general and local dynamic models without PLT, which uses indirect call via GOT: call *___tls_get_addr@GOT(%reg) where EBX register isn't required as GOT base, instead of direct call: call ___tls_get_addr[@PLT] which requires EBX register as GOT base. Since direct call is 4-byte long and indirect call, is 5-byte long, the extra one byte must be handled properly. For general dynamic model, 7-byte lea instruction before call instruction is replaced by 6-byte one to make room for indirect call. For local dynamic model, we simply use 5-byte indirect call. TLS linker optimization is updated to recognize new instruction patterns. For local dynamic model to local exec model transition, we generate a 6-byte lea instruction as nop, instead of a 1-byte nop plus a 4-byte lea instruction. Since linker may convert call ___tls_get_addr[@PLT] to addr32 call ____tls_get_addr when producing static executable, both patterns are recognized. bfd/ * elf64-i386.c (elf_i386_link_hash_entry): Add tls_get_addr. (elf_i386_link_hash_newfunc): Initialize tls_get_addr to 2. (elf_i386_check_tls_transition): Check indirect call and direct call with the addr32 prefix for general and local dynamic models. Set the tls_get_addr feild. (elf_i386_convert_load_reloc): Always use addr32 prefix for indirect ___tls_get_addr call via GOT. (elf_i386_relocate_section): Handle GD->LE, GD->IE and LD->LE transitions with indirect call and direct call with the addr32 prefix. ld/ * testsuite/ld-i386/i386.exp: Run libtlspic2.so, tlsbin2, tlsgd3, tlsld2, tlsgd4, tlspie3a, tlspie3b and tlspie3c. * testsuite/ld-i386/pass.out: New file. * testsuite/ld-i386/tls-def1.c: Likewise. * testsuite/ld-i386/tls-gd1.S: Likewise. * testsuite/ld-i386/tls-ld1.S: Likewise. * testsuite/ld-i386/tls-main1.c: Likewise. * testsuite/ld-i386/tls.exp: Likewise. * testsuite/ld-i386/tlsbin2-nacl.rd: Likewise. * testsuite/ld-i386/tlsbin2.dd: Likewise. * testsuite/ld-i386/tlsbin2.rd: Likewise. * testsuite/ld-i386/tlsbin2.sd: Likewise. * testsuite/ld-i386/tlsbin2.td: Likewise. * testsuite/ld-i386/tlsbinpic2.s: Likewise. * testsuite/ld-i386/tlsgd3.dd: Likewise. * testsuite/ld-i386/tlsgd3.s: Likewise. * testsuite/ld-i386/tlsgd4.d: Likewise. * testsuite/ld-i386/tlsgd4.s: Likewise. * testsuite/ld-i386/tlsld2.s: Likewise. * testsuite/ld-i386/tlspic2-nacl.rd: Likewise. * testsuite/ld-i386/tlspic2.dd: Likewise. * testsuite/ld-i386/tlspic2.rd: Likewise. * testsuite/ld-i386/tlspic2.sd: Likewise. * testsuite/ld-i386/tlspic2.td: Likewise. * testsuite/ld-i386/tlspic3.s: Likewise. * testsuite/ld-i386/tlspie3.s: Likewise. * testsuite/ld-i386/tlspie3a.d: Likewise. * testsuite/ld-i386/tlspie3b.d: Likewise. * testsuite/ld-i386/tlspie3c.d: Likewise.
2016-06-08Support any relocation orderH.J. Lu8-23/+34
* testsuite/ld-x86-64/no-plt-1a.rd: Support any relocation order. * testsuite/ld-x86-64/no-plt-1b.rd: Likewise. * testsuite/ld-x86-64/no-plt-1c.rd: Likewise. * testsuite/ld-x86-64/no-plt-1d.rd: Likewise. * testsuite/ld-x86-64/no-plt-1e.rd: Likewise. * testsuite/ld-x86-64/no-plt-1f.rd: Likewise. * testsuite/ld-x86-64/no-plt-1g.rd: Likewise. * testsuite/ld-x86-64/no-plt.exp: Fix a typo.
2016-06-08Add missing ChangeLog entriesH.J. Lu1-0/+24
2016-06-08X86-64: Test external function reference without PLTH.J. Lu21-0/+557
To call an external function, the direct branch to the PLT entry can be replaced by an indirect branch via the GOT slot, which is similar to the first instruction in the PLT slot. Instead using the PLT slot as function address, the function address is retrieved from the GOT slot. If linker determines the function is defined locally, it converts indirect branch via the GOT slot to direct branch with a nop prefix and converts load via the GOT slot to load immediate or lea, * testsuite/ld-x86-64/libno-plt-1b.dd: Likewise. * testsuite/ld-x86-64/libno-plt-1b.rd: Likewise. * testsuite/ld-x86-64/no-plt-1a.dd: Likewise. * testsuite/ld-x86-64/no-plt-1a.rd: Likewise. * testsuite/ld-x86-64/no-plt-1b.dd: Likewise. * testsuite/ld-x86-64/no-plt-1b.rd: Likewise. * testsuite/ld-x86-64/no-plt-1c.dd: Likewise. * testsuite/ld-x86-64/no-plt-1c.rd: Likewise. * testsuite/ld-x86-64/no-plt-1d.dd: Likewise. * testsuite/ld-x86-64/no-plt-1d.rd: Likewise. * testsuite/ld-x86-64/no-plt-1e.dd: Likewise. * testsuite/ld-x86-64/no-plt-1e.rd: Likewise. * testsuite/ld-x86-64/no-plt-1f.dd: Likewise. * testsuite/ld-x86-64/no-plt-1f.rd: Likewise. * testsuite/ld-x86-64/no-plt-1g.dd: Likewise. * testsuite/ld-x86-64/no-plt-1g.rd: Likewise. * testsuite/ld-x86-64/no-plt-check1.S: Likewise. * testsuite/ld-x86-64/no-plt.exp: Likewise. * testsuite/ld-x86-64/no-plt-extern1.S: Likewise. * testsuite/ld-x86-64/no-plt-func1.c: Likewise. * testsuite/ld-x86-64/no-plt-main1.c: Likewise.
2016-06-07ld/testsuite/ld-elf/init-fini-arrays.d: Remove `ft32-*-*' xfailMaciej W. Rozycki2-2/+6
Revert the addition of `ft32-*-*' to this test case made with commit d1f70bdcab6c ("Fix lots of linker testsuite failures for the FT32 target.") as this case scores an XPASS now. ld/ * testsuite/ld-elf/init-fini-arrays.d: Remove `ft32-*-*' xfail.
2016-06-07Fix PLT first entry GOT operand calculation.Andreas Krebbel5-0/+66
Embedding the .plt section in another revealed a bug in the way the larl operand of the first magic plt entry is being calculated. Fixed with the attached patch. bfd/ChangeLog: * elf64-s390.c (elf_s390_finish_dynamic_sections): Subtract plt section offset when calculation the larl operand in the first PLT entry. ld/ChangeLog: * testsuite/ld-s390/pltoffset-1.dd: New test. * testsuite/ld-s390/pltoffset-1.ld: New test. * testsuite/ld-s390/pltoffset-1.s: New test. * testsuite/ld-s390/s390.exp: Run new test.
2016-06-07PowerPC VLEAlan Modra4-3/+16
VLE is an encoding, not a particular processor architecture, so it isn't really proper to select insns based on PPC_OPCODE_VLE. For example {"evaddw", VX (4, 512), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, {"vaddubs", VX (4, 512), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, shows two insns that have the same encoding, both available with VLE. Enabling both with VLE means we can't disassemble the second variant even if -Maltivec is given rather than -Mspe. Also, we don't check user assembly against the processor type as well as we could. Another problem is that when using the VLE encoding, insns from the main ppc opcode table are not available, except those using opcode 4 and 31. Correcting this revealed two errors in the ld testsuite, use of "nop" and "rfmci" when -mvle. This patch fixes those problems in the opcode table, and removes PPCNONE. I find a plain 0 distracts less from other values. In addition, I've implemented code to recognize some machine values from the apuinfo note present in ppc32 objects. It's not a complete disambiguation since we're lacking info to detect newer chips, but what we have should help with disassembly. include/ * elf/ppc.h (APUINFO_SECTION_NAME, APUINFO_LABEL, PPC_APUINFO_ISEL, PPC_APUINFO_PMR, PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK, PPC_APUINFO_SPE, PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK, PPC_APUINFO_VLE: Define. opcodes/ * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default cpu for "vle" to e500. * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE. (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise. (PPCNONE): Delete, substitute throughout. (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated" except for major opcode 4 and 31. (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags. bfd/ * cpu-powerpc.c (powerpc_compatible): Allow bfd_mach_ppc_vle entry to match other 32-bit archs. * elf32-ppc.c (_bfd_elf_ppc_set_arch): New function. (ppc_elf_object_p): Call it. (ppc_elf_special_sections): Use APUINFO_SECTION_NAME. Fix overlong line. (APUINFO_SECTION_NAME, APUINFO_LABEL): Don't define here. * elf64-ppc.c (ppc64_elf_object_p): Call _bfd_elf_ppc_set_arch. * bfd-in.h (_bfd_elf_ppc_at_tls_transform, _bfd_elf_ppc_at_tprel_transform): Move to.. * elf-bfd.h: ..here. (_bfd_elf_ppc_set_arch): Declare. * bfd-in2.h: Regenerate. gas/ * config/tc-ppc.c (PPC_APUINFO_ISEL, PPC_APUINFO_PMR, PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK, PPC_APUINFO_SPE, PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK, PPC_APUINFO_VLE): Don't define. (ppc_setup_opcodes): Check vle disables powerpc_opcodes overridden by vle_opcodes, and that vle flag doesn't enable opcodes. Don't add vle_opcodes twice. (ppc_cleanup): Use APUINFO_SECTION_NAME and APUINFO_LABEL. ld/ * testsuite/ld-powerpc/apuinfo1.s: Delete nop. * testsuite/ld-powerpc/apuinfo-vle2.s: New. * testsuite/ld-powerpc/powerpc.exp: Use apuinfo-vle2.s.
2016-06-06Support x86-64 TLS code sequences without PLTH.J. Lu46-5/+2527
We can generate x86-64 TLS code sequences for general and local dynamic models without PLT, which uses indirect call via GOT: call *__tls_get_addr@GOTPCREL(%rip) instead of direct call: call __tls_get_addr[@PLT] Since direct call is 4-byte long and indirect call, is 5-byte long, the extra one byte must be handled properly. For general dynamic model, one 0x66 prefix before call instruction is removed to make room for indirect call. For local dynamic model, we simply use 5-byte indirect call. TLS linker optimization is updated to recognize new instruction patterns. For local dynamic model to local exec model transition, we generate 4 0x66 prefixes, instead of 3, before mov instruction in 64-bit and generate a 5-byte nop, instead of 4-byte, before mov instruction in 32-bit. Since linker may convert call *__tls_get_addr@GOTPCREL(%rip) to addr32 call __tls_get_addr when producing static executable, both patterns are recognized. bfd/ * elf64-x86-64.c (elf_x86_64_link_hash_entry): Add tls_get_addr. (elf_x86_64_link_hash_newfunc): Initialize tls_get_addr to 2. (elf_x86_64_check_tls_transition): Check indirect call and direct call with the addr32 prefix for general and local dynamic models. Set the tls_get_addr feild. (elf_x86_64_convert_load_reloc): Always use addr32 prefix for indirect __tls_get_addr call via GOT. (elf_x86_64_relocate_section): Handle GD->LE, GD->IE and LD->LE transitions with indirect call and direct call with the addr32 prefix. ld/ * testsuite/ld-x86-64/pass.out: New file. * testsuite/ld-x86-64/tls-def1.c: Likewise. * testsuite/ld-x86-64/tls-gd1.S: Likewise. * testsuite/ld-x86-64/tls-ld1.S: Likewise. * testsuite/ld-x86-64/tls-main1.c: Likewise. * testsuite/ld-x86-64/tls.exp: Likewise. * testsuite/ld-x86-64/tlsbin2-nacl.rd: Likewise. * testsuite/ld-x86-64/tlsbin2.dd: Likewise. * testsuite/ld-x86-64/tlsbin2.rd: Likewise. * testsuite/ld-x86-64/tlsbin2.sd: Likewise. * testsuite/ld-x86-64/tlsbin2.td: Likewise. * testsuite/ld-x86-64/tlsbinpic2.s: Likewise. * testsuite/ld-x86-64/tlsgd10.dd: Likewise. * testsuite/ld-x86-64/tlsgd10.s: Likewise. * testsuite/ld-x86-64/tlsgd11.dd: Likewise. * testsuite/ld-x86-64/tlsgd11.s: Likewise. * testsuite/ld-x86-64/tlsgd12.d: Likewise. * testsuite/ld-x86-64/tlsgd12.s: Likewise. * testsuite/ld-x86-64/tlsgd13.d: Likewise. * testsuite/ld-x86-64/tlsgd13.s: Likewise. * testsuite/ld-x86-64/tlsgd14.dd: Likewise. * testsuite/ld-x86-64/tlsgd14.s: Likewise. * testsuite/ld-x86-64/tlsgd5c.s: Likewise. * testsuite/ld-x86-64/tlsgd6c.s: Likewise. * testsuite/ld-x86-64/tlsgd9.dd: Likewise. * testsuite/ld-x86-64/tlsgd9.s: Likewise. * testsuite/ld-x86-64/tlsld4.dd: Likewise. * testsuite/ld-x86-64/tlsld4.s: Likewise. * testsuite/ld-x86-64/tlsld5.dd: Likewise. * testsuite/ld-x86-64/tlsld5.s: Likewise. * testsuite/ld-x86-64/tlsld6.dd: Likewise. * testsuite/ld-x86-64/tlsld6.s: Likewise. * testsuite/ld-x86-64/tlspic2-nacl.rd: Likewise. * testsuite/ld-x86-64/tlspic2.dd: Likewise. * testsuite/ld-x86-64/tlspic2.rd: Likewise. * testsuite/ld-x86-64/tlspic2.sd: Likewise. * testsuite/ld-x86-64/tlspic2.td: Likewise. * testsuite/ld-x86-64/tlspic3.s: Likewise. * testsuite/ld-x86-64/tlspie2.s: Likewise. * testsuite/ld-x86-64/tlspie2a.d: Likewise. * testsuite/ld-x86-64/tlspie2b.d: Likewise. * testsuite/ld-x86-64/tlspie2c.d: Likewise. * testsuite/ld-x86-64/tlsgd5.dd: Updated. * testsuite/ld-x86-64/tlsgd6.dd: Likewise. * testsuite/ld-x86-64/x86-64.exp: Run libtlspic2.so, tlsbin2, tlsgd5b, tlsgd6b, tlsld4, tlsld5, tlsld6, tlsgd9, tlsgd10, tlsgd11, tlsgd14, tlsgd12, tlsgd13, tlspie2a, tlspie2b and tlspie2c.
2016-06-062016-06-06 Christian Groessler <chris@groessler.org>Christian Groessler1-60/+59
* ChangeLog: Fix entry from 2016-06-04.
2016-06-04ld/testsuite/ld-z8k/test-ld.sh: Remove. Checked in by mistake.Christian Groessler1-19/+0
2016-06-04Add z8k ld testsuite and fix range check in coff-z8k.cChristian Groessler61-0/+9981
bfd/ * coff-z8k.c (extra_case): Fix range check for R_JR relocation. ld/ * ld/testsuite/ld-z8k/0filler.s: New file. * ld/testsuite/ld-z8k/branch-target.s: New file. * ld/testsuite/ld-z8k/branch-target2.s: New file. * ld/testsuite/ld-z8k/calr-back-8001.d: New file. * ld/testsuite/ld-z8k/calr-back-8002.d: New file. * ld/testsuite/ld-z8k/calr-back-fail-8001.d: New file. * ld/testsuite/ld-z8k/calr-back-fail-8002.d: New file. * ld/testsuite/ld-z8k/calr-forw-8001.d: New file. * ld/testsuite/ld-z8k/calr-forw-8002.d: New file. * ld/testsuite/ld-z8k/calr-forw-fail-8001.d: New file. * ld/testsuite/ld-z8k/calr-forw-fail-8002.d: New file. * ld/testsuite/ld-z8k/calr-opcode.s: New file. * ld/testsuite/ld-z8k/dbjnz-forw-8001.d: New file. * ld/testsuite/ld-z8k/dbjnz-forw-8002.d: New file. * ld/testsuite/ld-z8k/dbjnz-forw-fail-8001.d: New file. * ld/testsuite/ld-z8k/dbjnz-forw-fail-8002.d: New file. * ld/testsuite/ld-z8k/dbjnz-opcode.s: New file. * ld/testsuite/ld-z8k/djnz-back-8001.d: New file. * ld/testsuite/ld-z8k/djnz-back-8002.d: New file. * ld/testsuite/ld-z8k/djnz-back-fail-8001.d: New file. * ld/testsuite/ld-z8k/djnz-back-fail-8002.d: New file. * ld/testsuite/ld-z8k/djnz-forw-8001.d: New file. * ld/testsuite/ld-z8k/djnz-forw-8002.d: New file. * ld/testsuite/ld-z8k/djnz-forw-fail-8001.d: New file. * ld/testsuite/ld-z8k/djnz-forw-fail-8002.d: New file. * ld/testsuite/ld-z8k/djnz-opcode.s: New file. * ld/testsuite/ld-z8k/filler.s: New file. * ld/testsuite/ld-z8k/jr-back-8001.d: New file. * ld/testsuite/ld-z8k/jr-back-8002.d: New file. * ld/testsuite/ld-z8k/jr-back-fail-8001.d: New file. * ld/testsuite/ld-z8k/jr-back-fail-8002.d: New file. * ld/testsuite/ld-z8k/jr-forw-8001.d: New file. * ld/testsuite/ld-z8k/jr-forw-8002.d: New file. * ld/testsuite/ld-z8k/jr-forw-fail-8001.d: New file. * ld/testsuite/ld-z8k/jr-forw-fail-8002.d: New file. * ld/testsuite/ld-z8k/jr-opcode.s: New file. * ld/testsuite/ld-z8k/ldr-back-8001.d: New file. * ld/testsuite/ld-z8k/ldr-back-8002.d: New file. * ld/testsuite/ld-z8k/ldr-back-fail-8001.d: New file. * ld/testsuite/ld-z8k/ldr-back-fail-8002.d: New file. * ld/testsuite/ld-z8k/ldr-forw-8001.d: New file. * ld/testsuite/ld-z8k/ldr-forw-8002.d: New file. * ld/testsuite/ld-z8k/ldr-forw-fail-8001.d: New file. * ld/testsuite/ld-z8k/ldr-forw-fail-8002.d: New file. * ld/testsuite/ld-z8k/ldr-opcode.s: New file. * ld/testsuite/ld-z8k/ldrb-forw-8001.d: New file. * ld/testsuite/ld-z8k/ldrb-forw-8002.d: New file. * ld/testsuite/ld-z8k/ldrb-forw-fail-8001.d: New file. * ld/testsuite/ld-z8k/ldrb-forw-fail-8002.d: New file. * ld/testsuite/ld-z8k/ldrb-opcode.s: New file. * ld/testsuite/ld-z8k/ldrb-opcode2.s: New file. * ld/testsuite/ld-z8k/other-file.s: New file. * ld/testsuite/ld-z8k/reloc.dd: New file. * ld/testsuite/ld-z8k/reloc.ld: New file. * ld/testsuite/ld-z8k/relocseg.dd: New file. * ld/testsuite/ld-z8k/relocseg.ld: New file. * ld/testsuite/ld-z8k/relocseg1.dd: New file. * ld/testsuite/ld-z8k/test-ld.sh: New file. * ld/testsuite/ld-z8k/this-file.s: New file. * ld/testsuite/ld-z8k/z8k.exp: New file.
2016-06-03Update x86 linker tests for --disable-x86-relax-relocationsH.J. Lu14-19/+35
Pass -mrelax-relocations=yes to x86 linker tests, which require relax relocations, to support --disable-x86-relax-relocations. * testsuite/ld-i386/i386.exp: Assemble gotpc1.o and pr19319b.o with -mrelax-relocations=yes. * testsuite/ld-i386/lea1a.d (as): Add -mrelax-relocations=yes. * testsuite/ld-i386/lea1b.d (as): Likewise. * testsuite/ld-i386/lea1d.d (as): Likewise. * testsuite/ld-i386/lea1e.d (as): Likewise. * testsuite/ld-i386/lea1f.d (as): Likewise. * testsuite/ld-i386/load7.d (as): Likewise. * testsuite/ld-i386/mov1b.d (as): Likewise. * testsuite/ld-i386/pr19175.d (as): Likewise. * testsuite/ld-ifunc/ifunc-13-i386.d (as): Likewise. * testsuite/ld-ifunc/ifunc-21-i386.d (as): Likewise. * testsuite/ld-ifunc/ifunc-22-i386.d (as): Likewise. * testsuite/ld-x86-64/x86-64.exp: Assemble gotpcrel1a.o, gotpcrel1b.o and gotpcrel1c.o with -mrelax-relocations=yes.
2016-06-02Allow ARC Linux targets that do not use uclibc.Vineet Gupta2-1/+5
bfd * config.bfd: Replace -uclibc with *. gas * configure.tgt: Replace -uclibc with *. ld * configure.tgt: Replace -uclibc with *.
2016-05-28MIPS/BFD: Correctly handle `bfd_reloc_outofrange' with branchesMaciej W. Rozycki5-0/+68
Fix internal errors like: ld: BFD (GNU Binutils) 2.26.51.20160526 internal error, aborting at .../bfd/elfxx-mips.c:10278 in _bfd_mips_elf_relocate_section ld: Please report this bug. triggered by the `bfd_reloc_outofrange' condition on branch relocations. bfd/ * elfxx-mips.c (b_reloc_p): New function. (_bfd_mips_elf_relocate_section) <bfd_reloc_outofrange>: Handle branch relocations. ld/ * testsuite/ld-mips-elf/unaligned-branch.d: New test. * testsuite/ld-mips-elf/unaligned-branch.s: New test source. * testsuite/ld-mips-elf/unaligned-text.s: New test source. * testsuite/ld-mips-elf/mips-elf.exp: Run the new test.
2016-05-28MIPS/LD/testsuite: Rename `unaligned-syms' to `unaligned-data'Maciej W. Rozycki6-4/+13
ld/ * testsuite/ld-mips-elf/unaligned-syms.s: Rename to... * testsuite/ld-mips-elf/unaligned-data.s: ... this. * testsuite/ld-mips-elf/unaligned-ldpc-0.d: Adjust accordingly. * testsuite/ld-mips-elf/unaligned-ldpc-1.d: Likewise. * testsuite/ld-mips-elf/unaligned-lwpc-0.d: Likewise. * testsuite/ld-mips-elf/unaligned-lwpc-1.d: Likewise.
2016-05-28MIPS/BFD: Enable local R_MIPS_26 overflow detectionMaciej W. Rozycki8-0/+130
The original MIPS SVR4 psABI defines the calculation for the R_MIPS_26 relocation in a complex way, as follows[1]: Name Value Field Symbol Calculation R_MIPS_26 4 T-targ26 local (((A << 2) | \ (P & 0xf0000000)) + S) >> 2 4 T-targ26 external (sign-extend(A << 2) + S) >> 2 This is further clarified, by correcting typos (already applied in the excerpt above) in the 64-bit psABI extension[2]. A note is included in both documents to specify that for the purpose of relocation processing a local symbol is one with binding STB_LOCAL and type STT_SECTION, and otherwise, a symbol is external. We have both calculations implemented for the R_MIPS_26 relocation, and by extension also for the R_MIPS16_26 and R_MICROMIPS_26_S1 relocations, from now on collectively called jump relocations. However our code uses a different condition to tell local and external symbols apart, that is it only checks for the STB_LOCAL binding and ignores the symbol type, however for REL relocations only. The external calculation is used for all RELA jump relocations. In reality the difference matters for jump relocations referring local MIPS16 and, as from recent commit 44d3da233815 ("MIPS/GAS: Treat local jump relocs the same no matter if REL or RELA"), also local microMIPS symbols. Such relocations are not converted to refer to corresponding section symbols instead and retain the original local symbol reference. It can be inferred from the relocation calculation definitions that the addend is effectively unsigned for the local case and explicitly signed for the external case. With the REL relocation format it makes sense given the limited range provided for by the field being relocated: the use of an unsigned addend expands the range by one bit for the local case, because a negative offset from a section symbol makes no sense, and any usable negative offset from the original local symbol will have worked out positive if converted to a section-relative reference. In the external case a signed addend gives more flexibility as offsets both negative and positive can be used with a symbol. Any such offsets will typically have a small value. The inclusion of the (P & 0xf0000000) component, ORed in the calculation in the local case, seems questionable as bits 31:28 are not included in the relocatable field and are masked out as the relocation is applied. Their value is therefore irrelevant for output processing, the relocated field ends up the same regardless of their value. They could be used for overflow detection, however this is precluded by adding them to bits 31:28 of the symbol referred, as the sum will not correspond to the value calculated by the processor at run time whenever bits 31:28 of the symbol referred are not all zeros, even though it is valid as long they are the same as bits 31:28 of P. We deal with this problem by ignoring any overflow resulting from the local calculation. This however makes us miss genuine overflow cases, where 31:28 of the symbol referred are different from bits 31:28 of P, and non-functional code is produced. Given the situation, for the purpose of overflow detection we can change our code to follow the original psABI and only treat the in-place addend as unsigned in the section symbol case, permitting jumps to offsets 128MiB and above into section. Sections so large may be uncommon, but still a reasonable use case. On the other hand such large offsets from regular local symbols are not expected and it makes sense to support (possibly small) negative offsets instead, also in consistency with what we do for global symbols. Drop the (P & 0xf0000000) component then, treat the addend as signed with local non-section symbols and also detect an overflow in the result of such calculation with local symbols. NB it does not affect the value computed for the relocatable field, it only affects overflow detection. References: [1] "SYSTEM V APPLICATION BINARY INTERFACE, MIPS RISC Processor Supplement, 3rd Edition", Figure 4-11: "Relocation Types", p. 4-19 <http://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf> [2] "64-bit ELF Object File Specification, Draft Version 2.5", Table 32 "Relocation Types", p. 45 <http://techpubs.sgi.com/library/manuals/4000/007-4658-001/pdf/007-4658-001.pdf> bfd/ * elfxx-mips.c (mips_elf_calculate_relocation): <R_MIPS16_26> <R_MIPS_26, R_MICROMIPS_26_S1>: Drop the region bits of the reloc location from calculation, treat the addend as signed with local non-section symbols and enable overflow detection. ld/ * testsuite/ld-mips-elf/jal-global-overflow-0.d: New test. * testsuite/ld-mips-elf/jal-global-overflow-1.d: New test. * testsuite/ld-mips-elf/jal-local-overflow-0.d: New test. * testsuite/ld-mips-elf/jal-local-overflow-1.d: New test. * testsuite/ld-mips-elf/jal-global-overflow.s: New test source. * testsuite/ld-mips-elf/jal-local-overflow.s: New test source. * testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2016-05-28Return void from linker callbacksAlan Modra3-49/+39
The ldmain.c implementation of these linker callback functions always return true, so any code handling a false return is dead. What's more, some of the bfd backends abort if ever a false return is seen, and there seems to be some confusion in gdb's compile-object-load.c. The return value was never meant to be "oh yes, a multiple_definition error occurred", but rather "out of memory or other catastrophic failure". This patch removes the status return on the callbacks that always return true. I kept the return status for "notice" because that one does happen to need to return "out of memory". include/ * bfdlink.h (struct bfd_link_callbacks): Update comments. Return void from multiple_definition, multiple_common, add_to_set, constructor, warning, undefined_symbol, reloc_overflow, reloc_dangerous and unattached_reloc. bfd/ * aoutx.h: Adjust linker callback calls throughout file, removing dead code. * bout.c: Likewise. * coff-alpha.c: Likewise. * coff-arm.c: Likewise. * coff-h8300.c: Likewise. * coff-h8500.c: Likewise. * coff-i960.c: Likewise. * coff-mcore.c: Likewise. * coff-mips.c: Likewise. * coff-ppc.c: Likewise. * coff-rs6000.c: Likewise. * coff-sh.c: Likewise. * coff-tic80.c: Likewise. * coff-w65.c: Likewise. * coff-z80.c: Likewise. * coff-z8k.c: Likewise. * coff64-rs6000.c: Likewise. * cofflink.c: Likewise. * ecoff.c: Likewise. * elf-bfd.h: Likewise. * elf-m10200.c: Likewise. * elf-m10300.c: Likewise. * elf32-arc.c: Likewise. * elf32-arm.c: Likewise. * elf32-avr.c: Likewise. * elf32-bfin.c: Likewise. * elf32-cr16.c: Likewise. * elf32-cr16c.c: Likewise. * elf32-cris.c: Likewise. * elf32-crx.c: Likewise. * elf32-d10v.c: Likewise. * elf32-epiphany.c: Likewise. * elf32-fr30.c: Likewise. * elf32-frv.c: Likewise. * elf32-ft32.c: Likewise. * elf32-h8300.c: Likewise. * elf32-hppa.c: Likewise. * elf32-i370.c: Likewise. * elf32-i386.c: Likewise. * elf32-i860.c: Likewise. * elf32-ip2k.c: Likewise. * elf32-iq2000.c: Likewise. * elf32-lm32.c: Likewise. * elf32-m32c.c: Likewise. * elf32-m32r.c: Likewise. * elf32-m68hc1x.c: Likewise. * elf32-m68k.c: Likewise. * elf32-mep.c: Likewise. * elf32-metag.c: Likewise. * elf32-microblaze.c: Likewise. * elf32-moxie.c: Likewise. * elf32-msp430.c: Likewise. * elf32-mt.c: Likewise. * elf32-nds32.c: Likewise. * elf32-nios2.c: Likewise. * elf32-or1k.c: Likewise. * elf32-ppc.c: Likewise. * elf32-s390.c: Likewise. * elf32-score.c: Likewise. * elf32-score7.c: Likewise. * elf32-sh.c: Likewise. * elf32-sh64.c: Likewise. * elf32-spu.c: Likewise. * elf32-tic6x.c: Likewise. * elf32-tilepro.c: Likewise. * elf32-v850.c: Likewise. * elf32-vax.c: Likewise. * elf32-visium.c: Likewise. * elf32-xstormy16.c: Likewise. * elf32-xtensa.c: Likewise. * elf64-alpha.c: Likewise. * elf64-hppa.c: Likewise. * elf64-ia64-vms.c: Likewise. * elf64-mmix.c: Likewise. * elf64-ppc.c: Likewise. * elf64-s390.c: Likewise. * elf64-sh64.c: Likewise. * elf64-x86-64.c: Likewise. * elflink.c: Likewise. * elfnn-aarch64.c: Likewise. * elfnn-ia64.c: Likewise. * elfxx-mips.c: Likewise. * elfxx-sparc.c: Likewise. * elfxx-tilegx.c: Likewise. * linker.c: Likewise. * pdp11.c: Likewise. * pe-mips.c: Likewise. * reloc.c: Likewise. * reloc16.c: Likewise. * simple.c: Likewise. * vms-alpha.c: Likewise. * xcofflink.c: Likewise. * elf32-rl78.c (get_symbol_value, get_romstart, get_ramstart): Delete status param. Adjust calls to these and linker callbacks throughout. * elf32-rx.c: (get_symbol_value, get_gp, get_romstart, get_ramstart): Delete status param. Adjust calls to these and linker callbacks throughout. ld/ * ldmain.c (multiple_definition, multiple_common, add_to_set, constructor_callback, warning_callback, undefined_symbol, reloc_overflow, reloc_dangerous, unattached_reloc): Return void. * emultempl/elf32.em: Adjust callback calls. gdb/ * compile/compile-object-load.c (link_callbacks_multiple_definition, link_callbacks_warning, link_callbacks_undefined_symbol, link_callbacks_undefined_symbol, link_callbacks_reloc_overflow, link_callbacks_reloc_dangerous, link_callbacks_unattached_reloc): Return void.
2016-05-27MIPS/BFD: Include the addend in JALX's target alignment verificationMaciej W. Rozycki10-0/+239
On RELA targets the addend can affect JALX target's alignment, so only verify it once the whole relocation calculation has completed. bfd/ * elfxx-mips.c (mips_elf_calculate_relocation) <R_MIPS16_26> <R_MIPS_26, R_MICROMIPS_26_S1>: Include the addend in JALX's target alignment verification. ld/ * testsuite/ld-mips-elf/unaligned-jalx-addend-0.d: New test. * testsuite/ld-mips-elf/unaligned-jalx-addend-1.d: New test. * testsuite/ld-mips-elf/unaligned-jalx-addend-mips16-0.d: New test. * testsuite/ld-mips-elf/unaligned-jalx-addend-mips16-1.d: New test. * testsuite/ld-mips-elf/unaligned-jalx-addend-micromips-0.d: New test. * testsuite/ld-mips-elf/unaligned-jalx-addend-micromips-1.d: New test. * testsuite/ld-mips-elf/unaligned-jalx-addend-0.s: New test source. * testsuite/ld-mips-elf/unaligned-jalx-addend-1.s: New test source. * testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2016-05-27MIPS/BFD: Fix section symbol name fetching in relocationMaciej W. Rozycki4-0/+24
Symbol table entries for section symbols are different between IRIX and traditional MIPS ELF targets in that IRIX entries have their `st_name' member pointing at the section's name in the string table section, while traditional entries have 0 there and the section header string table has to be referred via the relevant section header's `shn_name' member instead. This is chosen with the `elf_backend_name_local_section_symbols' backend and can be observed with `readelf -s' output for an IRIX object: Symbol table '.symtab' contains 12 entries: Num: Value Size Type Bind Vis Ndx Name 0: 00000000 0 NOTYPE LOCAL DEFAULT UND 1: 00000000 0 SECTION LOCAL DEFAULT 1 .text 2: 00000000 0 SECTION LOCAL DEFAULT 3 .data 3: 00000000 0 SECTION LOCAL DEFAULT 4 .bss 4: 00000000 0 SECTION LOCAL DEFAULT 5 .reginfo 5: 00000000 0 SECTION LOCAL DEFAULT 6 .MIPS.abiflags 6: 00000000 0 SECTION LOCAL DEFAULT 7 .pdr 7: 00000000 0 SECTION LOCAL DEFAULT 9 .gnu.attributes 8: 00002000 16 FUNC GLOBAL DEFAULT 1 foo 9: 00004008 0 FUNC LOCAL DEFAULT 1 abar 10: 00002008 0 FUNC LOCAL DEFAULT 1 afoo 11: 00004000 16 FUNC GLOBAL DEFAULT 1 bar and a corresponding traditional object: Symbol table '.symtab' contains 12 entries: Num: Value Size Type Bind Vis Ndx Name 0: 00000000 0 NOTYPE LOCAL DEFAULT UND 1: 00000000 0 SECTION LOCAL DEFAULT 1 2: 00000000 0 SECTION LOCAL DEFAULT 3 3: 00000000 0 SECTION LOCAL DEFAULT 4 4: 00004008 0 FUNC LOCAL DEFAULT 1 abar 5: 00002008 0 FUNC LOCAL DEFAULT 1 afoo 6: 00000000 0 SECTION LOCAL DEFAULT 5 7: 00000000 0 SECTION LOCAL DEFAULT 6 8: 00000000 0 SECTION LOCAL DEFAULT 7 9: 00000000 0 SECTION LOCAL DEFAULT 9 10: 00002000 16 FUNC GLOBAL DEFAULT 1 foo 11: 00004000 16 FUNC GLOBAL DEFAULT 1 bar respectively. Consequently the right way to retrieve a section symbol's name has to be chosen in `mips_elf_calculate_relocation' for the purpose of error reporting. Originally we produced symbol tables in the traditional object format only and we handled it correctly until it was lost in a rewrite with: commit 7403cb6305f5660fccc8869d3333a731102ae978 Author: Mark Mitchell <mark@codesourcery.com> Date: Wed Jun 30 20:13:43 1999 +0000 probably because of the extra pointer indirection added which made the same expression have a different meaning. With the addition of IRIX symbol table format with: commit 174fd7f9556183397625dbfa99ef68ecd325c74b Author: Richard Sandiford <rdsandiford@googlemail.com> Date: Mon Feb 9 08:04:00 2004 +0000 the bug has been partially covered and now when a relocation error is triggered with an IRIX object the offending section symbol is correctly reported: tmpdir/dump0.o: In function `foo': (.text+0x2000): relocation truncated to fit: R_MIPS_26 against `.text' tmpdir/dump0.o: In function `bar': (.text+0x4000): relocation truncated to fit: R_MIPS_26 against `.text' because `bfd_elf_string_from_elf_section' retrieves the name from the string table section. With a traditional object however the function returns an empty string and consequently `no symbol' is printed instead: tmpdir/dump0.o: In function `foo': (.text+0x2000): relocation truncated to fit: R_MIPS_26 against `no symbol' tmpdir/dump0.o: In function `bar': (.text+0x4000): relocation truncated to fit: R_MIPS_26 against `no symbol' Restore the original semantics so that the section name is always correctly retrieved. bfd/ * elfxx-mips.c (mips_elf_calculate_relocation): Also use the section name if `bfd_elf_string_from_elf_section' returns an empty string. ld/ * testsuite/ld-mips-elf/reloc-local-overflow.d: New test. * testsuite/ld-mips-elf/reloc-local-overflow.s: Source for the new test. * testsuite/ld-mips-elf/mips-elf.exp: Run the new test.
2016-05-26MIPS/BFD: Don't stop processing on `bfd_reloc_outofrange'Maciej W. Rozycki31-193/+65
Upon a `bfd_reloc_outofrange' error continue processing so that any further issues are also reported, similarly to how `bfd_reloc_overflow' is handled. Adjust message formatting accordingly, using `%X' to abort processing at conclusion. Reduce the number of test cases by grouping relocations the handling of which can now be verified together with a single source and dump. bfd/ * elfxx-mips.c (_bfd_mips_elf_relocate_section) <bfd_reloc_outofrange>: Use the `%X%H' rather than `%C' format for message. Continue processing rather than returning failure. ld/ * testsuite/ld-mips-elf/unaligned-jalx-0.d: Fold `unaligned-jalx-2' here. * testsuite/ld-mips-elf/unaligned-jalx-mips16-0.d: Fold `unaligned-jalx-mips16-2' here. * testsuite/ld-mips-elf/unaligned-jalx-micromips-0.d: Fold `unaligned-jalx-micromips-2' here. * testsuite/ld-mips-elf/unaligned-jalx-0.s: Update accordingly. * testsuite/ld-mips-elf/unaligned-jalx-1.d: Update error message. * testsuite/ld-mips-elf/unaligned-jalx-mips16-1.d: Likewise. * testsuite/ld-mips-elf/unaligned-jalx-micromips-1.d: Likewise. * testsuite/ld-mips-elf/unaligned-jalx-2.d: Remove test. * testsuite/ld-mips-elf/unaligned-jalx-mips16-2.d: Remove test. * testsuite/ld-mips-elf/unaligned-jalx-micromips-2.d: Remove test. * testsuite/ld-mips-elf/unaligned-jalx-2.s: Remove test source. * testsuite/ld-mips-elf/unaligned-lwpc-0.d: Fold `unaligned-lwpc-3' here. * testsuite/ld-mips-elf/unaligned-lwpc-0.s: Update accordingly. * testsuite/ld-mips-elf/unaligned-lwpc-1.d: Fold `unaligned-lwpc-2' here. * testsuite/ld-mips-elf/unaligned-lwpc-1.s: Update accordingly. * testsuite/ld-mips-elf/unaligned-lwpc-2.d: Remove test. * testsuite/ld-mips-elf/unaligned-lwpc-2.s: Remove test source. * testsuite/ld-mips-elf/unaligned-lwpc-3.d: Remove test. * testsuite/ld-mips-elf/unaligned-lwpc-3.s: Remove test source. * testsuite/ld-mips-elf/unaligned-ldpc-0.d: Fold `unaligned-ldpc-4' here. * testsuite/ld-mips-elf/unaligned-ldpc-0.s: Update accordingly. * testsuite/ld-mips-elf/unaligned-ldpc-1.d: Update error message. Fold `unaligned-ldpc-2' and `unaligned-ldpc-3' here. * testsuite/ld-mips-elf/unaligned-ldpc-1.s: Update accordingly. * testsuite/ld-mips-elf/unaligned-ldpc-2.d: Remove test. * testsuite/ld-mips-elf/unaligned-ldpc-2.s: Remove test source. * testsuite/ld-mips-elf/unaligned-ldpc-3.d: Remove test. * testsuite/ld-mips-elf/unaligned-ldpc-3.s: Remove test source. * testsuite/ld-mips-elf/unaligned-ldpc-4.d: Remove test. * testsuite/ld-mips-elf/unaligned-ldpc-4.s: Remove test source. * testsuite/ld-mips-elf/mips-elf.exp: Delete removed tests.
2016-05-26Provide the __bssstart and __bsssize symbols needed by the MSP430's crt0.o code.Nick Clifton3-2/+13
PR target/20134 * scripttempl/elf32msp430.sc (.bss): Provide __bssstart and __bsssize. * scripttempl/elf32msp430_3.sc (.bss): Likewise.
2016-05-25MIPS/BFD: Report `bfd_reloc_outofrange' errors as suchMaciej W. Rozycki34-0/+456
A `bfd_reloc_outofrange' condition from `mips_elf_calculate_relocation' currently triggers the warning callback, which in the case of LD prints messages like: foo.o: In function `foo': (.text+0x0): warning: JALX to a non-word-aligned address or: foo.o: In function `foo': (.text+0x0): warning: PC-relative load from unaligned address and nothing else, which suggests this is a benign condition and link has otherwise successfully run to completion. This is however not the case, the link terminates right away with no further messages and no output produced. Use the general error or warning info callback then, preserving the message format. Also set a BFD error condition so that a failure is unambiguously reported. Complement the change with a set of suitable test suite additions. bfd/ * elfxx-mips.c (_bfd_mips_elf_relocate_section) <bfd_reloc_outofrange>: Call `->einfo' rather than `->warning'. Call `bfd_set_error'. ld/ * testsuite/ld-mips-elf/unaligned-jalx-0.d: New test. * testsuite/ld-mips-elf/unaligned-jalx-1.d: New test. * testsuite/ld-mips-elf/unaligned-jalx-2.d: New test. * testsuite/ld-mips-elf/unaligned-jalx-mips16-0.d: New test. * testsuite/ld-mips-elf/unaligned-jalx-mips16-1.d: New test. * testsuite/ld-mips-elf/unaligned-jalx-mips16-2.d: New test. * testsuite/ld-mips-elf/unaligned-jalx-micromips-0.d: New test. * testsuite/ld-mips-elf/unaligned-jalx-micromips-1.d: New test. * testsuite/ld-mips-elf/unaligned-jalx-micromips-2.d: New test. * testsuite/ld-mips-elf/unaligned-lwpc-0.d: New test. * testsuite/ld-mips-elf/unaligned-lwpc-1.d: New test. * testsuite/ld-mips-elf/unaligned-lwpc-2.d: New test. * testsuite/ld-mips-elf/unaligned-lwpc-3.d: New test. * testsuite/ld-mips-elf/unaligned-ldpc-0.d: New test. * testsuite/ld-mips-elf/unaligned-ldpc-1.d: New test. * testsuite/ld-mips-elf/unaligned-ldpc-2.d: New test. * testsuite/ld-mips-elf/unaligned-ldpc-3.d: New test. * testsuite/ld-mips-elf/unaligned-ldpc-4.d: New test. * testsuite/ld-mips-elf/unaligned-jalx-0.s: New test source. * testsuite/ld-mips-elf/unaligned-jalx-1.s: New test source. * testsuite/ld-mips-elf/unaligned-jalx-2.s: New test source. * testsuite/ld-mips-elf/unaligned-insn.s: New test source. * testsuite/ld-mips-elf/unaligned-lwpc-0.s: New test source. * testsuite/ld-mips-elf/unaligned-lwpc-1.s: New test source. * testsuite/ld-mips-elf/unaligned-lwpc-2.s: New test source. * testsuite/ld-mips-elf/unaligned-lwpc-3.s: New test source. * testsuite/ld-mips-elf/unaligned-ldpc-0.s: New test source. * testsuite/ld-mips-elf/unaligned-ldpc-1.s: New test source. * testsuite/ld-mips-elf/unaligned-ldpc-2.s: New test source. * testsuite/ld-mips-elf/unaligned-ldpc-3.s: New test source. * testsuite/ld-mips-elf/unaligned-ldpc-4.s: New test source. * testsuite/ld-mips-elf/unaligned-syms.s: New test source. * testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2016-05-25Skip an archive element if not added by linkerH.J. Lu7-3/+126
During archive rescan to resolve symbol references for files added by LTO, linker add_archive_element callback is called to check if an archive element should added. After all IR symbols have been claimed, linker won't claim new IR symbols and shouldn't add the LTO archive element. This patch updates linker add_archive_element callback to return FALSE when seeing an LTO archive element during rescan and changes ELF linker to skip such archive element. bfd/ PR ld/20103 * cofflink.c (coff_link_check_archive_element): Return TRUE if linker add_archive_element callback returns FALSE. * ecoff.c (ecoff_link_check_archive_element): Likewise. * elf64-ia64-vms.c (elf64_vms_link_add_archive_symbols): Skip archive element if linker add_archive_element callback returns FALSE. * elflink.c (elf_link_add_archive_symbols): Likewise. * pdp11.c (aout_link_check_ar_symbols): Likewise. * vms-alpha.c (alpha_vms_link_add_archive_symbols): Likewise. * xcofflink.c (xcoff_link_check_dynamic_ar_symbols): Likewise. (xcoff_link_check_ar_symbols): Likewise. ld/ PR ld/20103 * ldmain.c (add_archive_element): Don't claim new IR symbols after all IR symbols have been claimed. * plugin.c (plugin_call_claim_file): Remove no_more_claiming check. * testsuite/ld-plugin/lto.exp (pr20103): New proc. Run PR ld/20103 tests. * testsuite/ld-plugin/pr20103a.c: New file. * testsuite/ld-plugin/pr20103b.c: Likewise. * testsuite/ld-plugin/pr20103c.c: Likewise.
2016-05-24MIPS/GAS: Treat local jump relocs the same no matter if REL or RELAMaciej W. Rozycki5-0/+48
Do not convert jump relocs against local MIPS16 or microMIPS symbols to refer to a section symbol instead even on RELA targets, as it makes it impossible for the linker to make a JAL to JALX conversion based on ISA symbol annotation, breaking regular and compressed MIPS interlinking. gas/ * config/tc-mips.c (mips_fix_adjustable): Also return 0 for jump relocations against MIPS16 or microMIPS symbols on RELA targets. * testsuite/gas/mips/jalx-local.d: New test. * testsuite/gas/mips/jalx-local-n32.d: New test. * testsuite/gas/mips/jalx-local-n64.d: New test. * testsuite/gas/mips/jalx-local.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. ld/ * testsuite/ld-mips-elf/jalx-local.d: New test. * testsuite/ld-mips-elf/jalx-local-n32.d: New test. * testsuite/ld-mips-elf/jalx-local-n64.d: New test. * testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
generated by cgit v1.1 at 2024-11-25 12:33:07 +0000