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2023-12-29LoongArch: ld: Add support for tls le relax.changjiachen6-1/+320
Add tls le relax related testsuites in ld. The new test cases are mainly tested in three aspects: 1. tls le relax function correctness test. 2. tls le relax boundary check test. 3. tls le relax function compatibility test. ld/testsuite/ChangeLog: * ld/testsuite/ld-loongarch-elf/relax.exp: Modify test. * ld/testsuite/ld-loongarch-elf/old-tls-le.s: New test. * ld/testsuite/ld-loongarch-elf/relax-bound-check-tls-le.s: Likewise. * ld/testsuite/ld-loongarch-elf/tls-relax-compatible-check-new.s: Likewise. * ld/testsuite/ld-loongarch-elf/relax-tls-le.s: Likewise. * ld/testsuite/ld-loongarch-elf/tls-relax-compatible-check-old.s: Likewise.
2023-12-28x86-64: Add R_X86_64_CODE_4_GOTTPOFF/R_X86_64_CODE_4_GOTPC32_TLSDESCH.J. Lu3-18/+106
For add name@gottpoff(%rip), %reg mov name@gottpoff(%rip), %reg add # define R_X86_64_CODE_4_GOTTPOFF 44 and for lea name@tlsdesc(%rip), %reg add # define R_X86_64_CODE_4_GOTPC32_TLSDESC 45 if the instruction starts at 4 bytes before the relocation offset. They are similar to R_X86_64_GOTTPOFF and R_X86_64_GOTPC32_TLSDESC, respectively. Linker can covert GOTTPOFF to add $name@tpoff, %reg mov $name@tpoff, %reg and GOTPC32_TLSDESC to mov $name@tpoff, %reg mov name@gottpoff(%rip), %reg if the instruction is encoded with the REX2 prefix when possible. bfd/ * elf64-x86-64.c (x86_64_elf_howto_table): Add R_X86_64_CODE_4_GOTTPOFF and R_X86_64_CODE_4_GOTPC32_TLSDESC. (R_X86_64_standard): Updated. (x86_64_reloc_map): Add BFD_RELOC_X86_64_CODE_4_GOTTPOFF and BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC. (elf_x86_64_check_tls_transition): Handle R_X86_64_CODE_4_GOTTPOFF and R_X86_64_CODE_4_GOTPC32_TLSDESC. (elf_x86_64_tls_transition): Likewise. (elf_x86_64_scan_relocs): Likewise. (elf_x86_64_relocate_section): Likewise. * reloc.c (bfd_reloc_code_real): Add BFD_RELOC_X86_64_CODE_4_GOTTPOFF and BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC. * bfd-in2.h: Regenerated. * libbfd.h: Likewise. gas/ * config/tc-i386.c (tc_i386_fix_adjustable): Handle BFD_RELOC_X86_64_CODE_4_GOTTPOFF and BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC. (md_assemble): Handle BFD_RELOC_X86_64_CODE_4_GOTTPOFF. (output_insn): Don't add empty REX prefix with REX2 prefix. (output_disp): Handle BFD_RELOC_X86_64_CODE_4_GOTTPOFF and BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC. (md_apply_fix): Likewise. (i386_validate_fix): Generate BFD_RELOC_X86_64_CODE_4_GOTTPOFF or BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC if ixp->fx_tcbit3 is set. (tc_gen_reloc): Handle BFD_RELOC_X86_64_CODE_4_GOTTPOFF and BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC. * testsuite/gas/i386/x86-64-gottpoff.d: New file. * testsuite/gas/i386/x86-64-gottpoff.s: Likewise. * testsuite/gas/i386/x86-64-tlsdesc.d: Likewise. * testsuite/gas/i386/x86-64-tlsdesc.s: Likewise. include/ * elf/x86-64.h (elf_x86_64_reloc_type): Add R_X86_64_CODE_4_GOTTPOFF and R_X86_64_CODE_4_GOTPC32_TLSDESC ld/ * testsuite/ld-x86-64/tlsbindesc.d: Updated. * testsuite/ld-x86-64/tlsbindesc.rd: Likewise. * testsuite/ld-x86-64/tlsbindesc.s: Add R_X86_64_CODE_4_GOTTPOFF and R_X86_64_CODE_4_GOTPC32_TLSDESC tests.
2023-12-28x86-64: Add R_X86_64_CODE_4_GOTPCRELXH.J. Lu6-0/+258
For mov name@GOTPCREL(%rip), %reg test %reg, name@GOTPCREL(%rip) binop name@GOTPCREL(%rip), %reg where binop is one of adc, add, add, cmp, or, sbb, sub, xor instructions, add # define R_X86_64_CODE_4_GOTPCRELX 43 if the instruction starts at 4 bytes before the relocation offset. It similar to R_X86_64_GOTPCRELX. Linker can treat R_X86_64_CODE_4_GOTPCRELX as R_X86_64_GOTPCREL or convert the above instructions to lea name(%rip), %reg mov $name, %reg test $name, %reg binop $name, %reg if the instruction is encoded with the REX2 prefix when possible. bfd/ * elf64-x86-64.c (x86_64_elf_howto_table): Add R_X86_64_CODE_4_GOTPCRELX. (R_X86_64_standard): Updated. (x86_64_reloc_map): Add BFD_RELOC_X86_64_CODE_4_GOTPCRELX. (elf_x86_64_convert_load_reloc): Handle R_X86_64_CODE_4_GOTPCRELX. (elf_x86_64_scan_relocs): Likewise. (elf_x86_64_relocate_section): Likewise. * reloc.c (bfd_reloc_code_real): Add BFD_RELOC_X86_64_CODE_4_GOTPCRELX. * bfd-in2.h: Regenerated. * libbfd.h: Likewise. gas/ * write.h (fix): Add fx_tcbit3. Change fx_unused to 1 bit. * config/tc-i386.c (tc_i386_fix_adjustable): Handle BFD_RELOC_X86_64_CODE_4_GOTPCRELX. (tc_gen_reloc): Likewise. (output_disp): Set fixP->fx_tcbit3 for REX2 prefix. (i386_validate_fix): Generate BFD_RELOC_X86_64_CODE_4_GOTPCRELX if fixp->fx_tcbit3 is set. * config/tc-i386.h (TC_FORCE_RELOCATION_LOCAL): Add BFD_RELOC_X86_64_CODE_4_GOTPCRELX. (TC_FORCE_RELOCATION_ABS): Likewise. * testsuite/gas/i386/x86-64-gotpcrel.s: Add tests for R_X86_64_CODE_4_GOTPCRELX. * testsuite/gas/i386/x86-64-localpic.s: Likewise. * testsuite/gas/i386/x86-64-gotpcrel.d: Updated. * testsuite/gas/i386/x86-64-localpic.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-localpic.d: Likewise. include/ * elf/x86-64.h (elf_x86_64_reloc_type): Add R_X86_64_CODE_4_GOTPCRELX. ld/ * testsuite/ld-x86-64/apx-load1.s: New file. * testsuite/ld-x86-64/apx-load1a.d: Likewise. * testsuite/ld-x86-64/apx-load1b.d: Likewise. * testsuite/ld-x86-64/apx-load1c.d: Likewise. * testsuite/ld-x86-64/apx-load1d.d: Likewise. * testsuite/ld-x86-64/x86-64.exp: Run apx-load1a, apx-load1b, apx-load1c and apx-load1d.
2023-12-28RISC-V: PR31179, The SET/ADD/SUB fix breaks ABI compatibility with 2.41 objectsNelson Chu4-0/+36
* Problematic fix commit, 2029e13917d53d2289d3ebb390c4f40bd2112d21 RISC-V: Clarify the behaviors of SET/ADD/SUB relocations * Bugzilla, https://sourceware.org/bugzilla/show_bug.cgi?id=31179#c5 The addend of SUB_ULEB128 should be zero if using .uleb128, but we make it non-zero by accident in assembler before. This causes troubles by applying the above commit, since the calculation is changed to support .reloc *SUB* relocations with non-zero addend. We encourage people to rebuild their stuff to get the non-zero addend of SUB_ULEB128, but that might need some times, so report warnings to inform people need to rebuild their stuff if --check-uleb128 is enabled. Since the failed .reloc cases for ADD/SET/SUB/ULEB128 are rarely to use, it may acceptable that stop supproting them until people rebuld their stuff, maybe half-year or a year later. Or maybe we should teach people that don't write the .reloc R_RISCV_SUB* with non-zero constant, and then report warnings/errors in assembler. bfd/ * elfnn-riscv.c (perform_relocation): Ignore the non-zero addend of R_RISCV_SUB_ULEB128. (riscv_elf_relocate_section): Report warnings to inform people need to rebuild their stuff if --check-uleb128 is enabled. So that can get the right non-zero addend of R_RISCV_SUB_ULEB128. * elfxx-riscv.h (struct riscv_elf_params): Added bool check_uleb128. ld/ * NEWS: Updated. * emultempl/riscvelf.em: Added linker risc-v target options, --[no-]check-uleb128, to enable/disable checking if the addend of uleb128 is non-zero or not. So that people will know they need to rebuild the objects with binutils 2.42 and up, to get the right zero addend of SUB_ULEB128 relocation, or they may get troubles if using .reloc. * ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated. * ld/testsuite/ld-riscv-elf/pr31179*: New test cases.
2023-12-25LoongArch: Add testsuit for DESC and tls transition and tls relaxation.Lulu Cai13-0/+258
2023-12-25LoongArch: Add support for TLS LD/GD/DESC relaxationmengqinggang2-252/+259
The pcalau12i + addi.d of TLS LD/GD/DESC relax to pcaddi. Relaxation is only performed when the TLS model transition is not possible.
2023-12-22LoongArch: Add support for the third expression of .align for R_LARCH_ALIGNmengqinggang8-4/+35
If the symbol index is not zero, the addend is used to represent the first and the third expressions of the .align. The lowest 8 bits are used to represent the first expression. Other bits are used to represent the third expression. The addend of R_LARCH_ALIGN for ".align 5, ,4" is 0x405. The addend of R_LARCH_ALIGN for ".balign 32, ,4" is 0x405.
2023-12-18ld: Print 0 size in B and not in GBTorbjörn SVENSSON2-0/+2
When using --print-memory-usage, the printed size can be zero and in that case, the unit should be B and not GB. ld/ * ldlang.c (lang_print_memory_size) Print 0 B instead of 0 GB. * testsuite/ld-scripts/print-memory-usage-1.l: Validate emplty region. * testsuite/ld-scripts/print-memory-usage-1.t: Define empty region. Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
2023-12-18LoongArch: Add call36 and tail36 pseudo instructions for medium code modelmengqinggang1-0/+2
For tail36, it is necessary to explicitly indicate the temporary register. Therefore, the compiler and users will know that the tail will use a register. call36 func pcalau18i $ra, %call36(func) jirl $ra, $ra, 0; tail36 $t0, func pcalau18i $t0, %call36(func) jirl $zero, $t0, 0;
2023-12-18LoongArch: Add new relocation R_LARCH_CALL36mengqinggang2-0/+19
R_LARCH_CALL36 is used for medium code model function call pcaddu18i+jirl, and these two instructions must adjacent. The LoongArch ABI v2.20 at here: https://github.com/loongson/la-abi-specs.
2023-12-13Update Make const_1_mode print $1 in AT&T syntaxH.J. Lu1-1/+1
commit b70a487d5945b13e5ab503be4fc37b964819ec0e Author: Cui, Lili <lili.cui@intel.com> Date: Wed Dec 13 06:07:36 2023 +0000 Make const_1_mode print $1 in AT&T syntax changes disassembler output from d1 f8 sar %eax to d1 f8 sar $1,%eax Adjust pe-x86-64-6.od accordingly. * testsuite/ld-x86-64/pe-x86-64-6.od: Adjusted.
2023-12-11R_MICROMIPS_GPREL7_S2Alan Modra2-2/+2
This reloc is meant for the 16-bit LWGP instruction, 0x6400/0xfc00 match/mask encoding in `micromips_opcodes'. It is correctly specified to operate on a half-word by the howtos in elf32-mips.c, elfn32-mips.c and elf64-mips.c, but is incorrectly subject to shuffle/unshuffle in code like _bfd_mips_elf32_gprel16_reloc. Current behaviour when applying the reloc to .byte 0x11,0x22,0x33,0x44 is to apply the reloc to byte 0x22 when big-endian, and to byte 0x33 when little-endian. Big-endian behaviour is unchanged after this patch and little-endian correctly applies the reloc to byte 0x11. The patch also corrects REL addend extraction from section contents, and overflow checking. gold had all of the bfd problems with this reloc and additionally did not apply the rightshift by two. bfd/ * elfxx-mips.c (micromips_reloc_shuffle_p): Return false for R_MICROMIPS_GPREL7_S2. (mips_elf_calculate_relocation): Correct sign extension and overflow calculation for R_MICROMIPS_GPREL7_S2. (_bfd_mips_elf_relocate_section): Update small-data overflow message. gold/ * mips.cc (Mips_relocate_functions::should_shuffle_micromips_reloc): Return false for R_MICROMIPS_GPREL7_S2. (Mips_relocate_functions::mips_reloc_unshuffle): Update comment. (Mips_relocate_functions::relgprel): Remove R_MICROMIPS_GPREL7_S2 handling. (Mips_relocate_functions::relgprel7): New function. (Target_mips::Relocate::relocate): Adjust to suit. ld/ * testsuite/ld-mips-elf/reloc-4.d: Adjust expected error. * testsuite/ld-mips-elf/reloc-5.d: Likewise.
2023-12-05aarch64-elf: FAIL: indirect call stub to BTI stub relaxationAlan Modra1-26/+25
aarch64-elf fails the ld-aarch64/bfd-far-3.d test, due to the stubs being emitted in a different order to that of aarch64-linux. They are emitted in a different order due to stub names for local symbols having the section id in the stub name. aarch64-linux-ld generates one more section than aarch64-elf-ld. That section is .gnu.hash. So the stub names differ and are hashed to different slots in stub_hash_table. Fix this by running the test with --hash-style=sysv, and adjust expected output. I've also changed the branch over stubs emitted at the start of a group of stubs to not care about the symbol, for all groups not just the one that needed changing. * ld-aarch64/bti-far-3.d: Add --hash-style=sysv. Adjust expected output.
2023-12-01Fix ld/x86: reduce testsuite dependency on system object filesH.J. Lu1-10/+10
commit eab996435fe65a421541f59557c5f1fd427573a3 Author: Jan Beulich <jbeulich@suse.com> Date: Tue Nov 7 13:58:32 2023 +0100 ld/x86: reduce testsuite dependency on system object files changed some C compiler tests to assembler/linker tests which introduced 2 problems: 1. It broke x32 binutils tests since --64 was passed to assembler, but -m elf_x86_64 wasn't passed to linker. 2. -nostdlib was passed to C compiler driver to exclude standard run-time files which should be avoided with -r option for linker tests. Fix them by passing -m elf_x86_64 to linker and removing -nostdlib for linker tests with -r. PR ld/30722 * testsuite/ld-x86-64/x86-64.exp: Pass -m elf_x86_64 to linker for tests with --64. Remove -nostdlib for tests with -r.
2023-11-17LoongArch: Add more relaxation testcasesmengqinggang4-5/+103
1. .so relaxation testcase 2. ld --no-relax testcase 3. segment alignment testcase
2023-11-10Add ability to change linker warning messages into errors when reporting ↵Nick Clifton69-89/+89
executable stacks and/or executable segments. include * bfdlink.h (struct bfd_link_info): Update descriptions of the 'execstack', 'noexecstack' and 'warn_execstack' fields. Add 'error_exectack' and 'warn_is_error_for_rwx_segments' fields. bfd * elf.c (assign_file_positions_except_relocs): Turn warnings about executable segments into errors if so requested. * elflink.c (bfd_elf_size_dynamic_sections): Turn warnings about executable stacks into errors if so requested. ld * ldlex.h (enum option_values): Add OPTION_ERROR_EXECSTACK, OPTION_NO_ERROR_EXECSTACK, OPTION_WARN_EXECSTACK_OBJECTS, OPTION_ERROR_RWX_SEGMENTS and OPTION_NO_ERROR_RWX_SEGMENTS. (struct ld_option): Add new long options. (parse_args): Parse new long options. (elf_static_list_options): Display the new options. * ld.texi: Document the new command line options. * configure.ac (error-execstack): New configuration option. (error-rwx-segments): New configuration option. * emultempl/elf.em (_before_parse): Initialse the new linkinfo fields. * NEWS: Mention the new features. * config.in: Regenerate. * configure: Regenerate. * testsuite/ld-elf/commonpage2.d: Disable errors for RWX segments and/or executable stacks. * testsuite/ld-elf/elf.exp: Likewise. * testsuite/ld-elf/header.d: Likewise. * testsuite/ld-elf/loadaddr1.d: Likewise. * testsuite/ld-elf/loadaddr2.d: Likewise. * testsuite/ld-elf/maxpage4.d: Likewise. * testsuite/ld-elf/nobits-1.d: Likewise. * testsuite/ld-elf/note-1.d: Likewise. * testsuite/ld-elf/orphan-10.d: Likewise. * testsuite/ld-elf/orphan-11.d: Likewise. * testsuite/ld-elf/orphan-12.d: Likewise. * testsuite/ld-elf/orphan-5.d: Likewise. * testsuite/ld-elf/orphan-7.d: Likewise. * testsuite/ld-elf/orphan-8.d: Likewise. * testsuite/ld-elf/orphan-9.d: Likewise. * testsuite/ld-elf/orphan-region.d: Likewise. * testsuite/ld-elf/orphan.d: Likewise. * testsuite/ld-elf/pr19539.d: Likewise. * testsuite/ld-elf/pr26256-1a.d: Likewise. * testsuite/ld-elf/pr26907.d: Likewise. * testsuite/ld-elf/pr28597.d: Likewise. * testsuite/ld-elf/retain2.d: Likewise. * testsuite/ld-elf/shared.exp: Likewise. * testsuite/ld-elf/size-1.d: Likewise. * testsuite/ld-elf/textaddr7.d: Likewise. * testsuite/ld-elf/warn1.d: Likewise. * testsuite/ld-elf/warn2.d: Likewise. * testsuite/ld-i386/discarded1.d: Likewise. * testsuite/ld-i386/pr19175.d: Likewise. * testsuite/ld-i386/pr19539.d: Likewise. * testsuite/ld-i386/pr23189.d: Likewise. * testsuite/ld-plugin/lto-3r.d: Likewise. * testsuite/ld-plugin/lto-5r.d: Likewise. * testsuite/ld-plugin/lto.exp: Likewise. * testsuite/ld-powerpc/ppc476-shared.d: Likewise. * testsuite/ld-powerpc/ppc476-shared2.d: Likewise. * testsuite/ld-powerpc/pr28827-2.d: Likewise. * testsuite/ld-s390/s390.exp: Likewise. * testsuite/ld-scripts/align2a.d: Likewise. * testsuite/ld-scripts/align2b.d: Likewise. * testsuite/ld-scripts/align5.d: Likewise. * testsuite/ld-scripts/alignof.exp: Likewise. * testsuite/ld-scripts/crossref.exp: Likewise. * testsuite/ld-scripts/defined2.d: Likewise. * testsuite/ld-scripts/defined3.d: Likewise. * testsuite/ld-scripts/defined5.d: Likewise. * testsuite/ld-scripts/pr14962.d: Likewise. * testsuite/ld-scripts/pr18963.d: Likewise. * testsuite/ld-scripts/pr20302.d: Likewise. * testsuite/ld-scripts/print-memory-usage.exp: Likewise. * testsuite/ld-scripts/rgn-at1.d: Likewise. * testsuite/ld-scripts/rgn-at10.d: Likewise. * testsuite/ld-scripts/rgn-at4.d: Likewise. * testsuite/ld-scripts/rgn-at6.d: Likewise. * testsuite/ld-scripts/rgn-at8.d: Likewise. * testsuite/ld-scripts/rgn-at9.d: Likewise. * testsuite/ld-scripts/rgn-over1.d: Likewise. * testsuite/ld-scripts/rgn-over2.d: Likewise. * testsuite/ld-scripts/rgn-over4.d: Likewise. * testsuite/ld-scripts/rgn-over5.d: Likewise. * testsuite/ld-scripts/rgn-over6.d: Likewise. * testsuite/ld-scripts/script.exp: Likewise. * testsuite/ld-scripts/sizeof.exp: Likewise. * testsuite/ld-scripts/sort-file.d: Likewise. * testsuite/ld-x86-64/discarded1.d: Likewise. * testsuite/ld-x86-64/pr19175.d: Likewise. * testsuite/ld-x86-64/pr19539a.d: Likewise. * testsuite/ld-x86-64/pr19539b.d: Likewise. * testsuite/ld-x86-64/pr23189.d: Likewise.
2023-11-09ld: aarch64: Use lp64 abi in recent BTI stub testsSzabolcs Nagy5-8/+4
The tests are not compatible with ilp32 abi: the GNU property note is ABI dependent (size changes) and the disasm is ABI dependent too. Making the test portable between the ABIs is not trivial. For now force lp64 abi.
2023-11-09ld: aarch64: Add BTI stub insertion test PR30930Szabolcs Nagy6-0/+172
The test creates a large shared library and covers a number of BTI stub insertion cases.
2023-11-07ld/x86: reduce testsuite dependency on system object filesJan Beulich4-94/+131
PR ld/30722 Tests looking for certain .note-section recorded properties may not involve object files from the underlying platform (e.g. via using the C compiler for linking): Such object files may themselves have similar note sections, and hence they may influence the overall outcome. For now convert just the tests known to be affected by crt*.o coming with "ISA v3 needed" notes. Eventually other tests ought to be converted, too.
2023-11-07Revert "ld x86_64 tests: Accept x86-64-v3 as a needed ISA"Jan Beulich3-3/+3
This reverts commit bf77f42f6708d8b5ba92336d876042826d8d29c1. It wrongly altered testcase expectations; the issue will need taking care of differently.
2023-11-06ld: =fillexp different behaviors for hexidecimal literalNick Clifton3-0/+42
PR 30865 * ld.texi: Update description of the FILL command. * testsuite/ld-scripts/fill2.d: New test. * testsuite/ld-scripts/fill2.t: New test source. * testsuite/ld-scripts/data.exp: Run the new test.
2023-11-02ld x86_64 tests: Accept x86-64-v3 as a needed ISANick Clifton3-3/+3
* testsuite/ld-x86-64/property-3.r: Update regexp to allow for targets which support x86-64-v3. * testsuite/ld-x86-64/property-4.r: Likewise. * testsuite/ld-x86-64/property-5.r: Likewise.
2023-11-01ld: Support input section description keyword: REVERSENick Clifton10-0/+105
PR 27565 * ldlex.l: Add REVERSE. * ldgram.y: Allow REVERSE to be used wherever a sorting command can be used. * ld.h (struct wildcard_spec): Add 'reversed' field. * ldlang.h (lang_wild_statement_struct): Add 'filenames_reversed' field. * ldlang.c (compare_sections): Add reversed parameter. (wild_sort): Reverse the comparison if requested. (print_wild_statement): Handle the reversed field. * ld.texi: Document the new feature. * NEWS: Mention the new feature. * testsuite/ld-scripts/sort-file-reversed-1.d: New test driver. * testsuite/ld-scripts/sort-file-reversed-1.t: New test source. * testsuite/ld-scripts/sort-file-reversed-2.t: New test source. * testsuite/ld-scripts/sort-file-reversed-2.d: New test driver. * testsuite/ld-scripts/sort-sections-reversed-1.d: New test driver. * testsuite/ld-scripts/sort-sections-reversed-1.t: New test source. * testsuite/ld-scripts/sort-sections-reversed-2.t: New test source. * testsuite/ld-scripts/sort-sections-reversed-2.d: New test driver. * testsuite/ld-scripts/sort-sections-reversed-3.d: New test driver. * testsuite/ld-scripts/sort-sections-reversed-3.t: New test source.
2023-10-13ld: allow update of existing QNX stack noteClément Chigot3-0/+27
Up to now, the linker would always create a QNX stack note from scratch. However, object files could already have such note, ending up into duplicates. QNX loader doesn't handle that. Update the mechanism to first search through the input files for a .note section holding a QNX stack note. If none are found, then a new section is created into the stub file as before. This requires this search to be done once the file have been opened, moving the whole logic a bit later in the emulation process. As part for this update, also allow to request an executable stack without necessarily having to provide its size as well. In this case, s etup a default lazy stack of 0x1000. ld/ChangeLog: * emultempl/nto.em (nto_create_QNX_note_section): New Function. (nto_lookup_QNX_note_section): New Function. (nto_add_note_section): Move the creation of the note section in the above new functions. (nto_create_output_section_statements): rename nto_after_open * testsuite/ld-aarch64/aarch64-nto.exp: add new test. * testsuite/ld-aarch64/nto-stack-note-3.d: New test. * testsuite/ld-aarch64/nto-stack-note.s: New test.
2023-10-05Fix: ld: Test case pr28158 fails on x86_64-linux-musl when index is > 19A. Wilcox1-1/+1
PR 30905 * testsuite/ld-elf/pr28158.rd: Adjust regexp to allow for section indicies larger than 9.
2023-10-05Fix: ld testsuite: glibc-specific DT_RELR tests should not be run on musl ↵A. Wilcox1-0/+4
systems PR 30917 * testsuite/ld-elf/dt-relr.exp: Skip for MUSL targets.
2023-10-05Fix: ld testsuite: non-PIC shared tests fail on powerpc-linux-muslA. Wilcox1-0/+2
PR 30918 * testsuite/ld-shared/shared.exp: Add XFAILs for tests that fail with the MUSL library.
2023-10-05Fix: ld testsuite: Thumb PLT and GOT tests should be skipped on musl armhf ↵A. Wilcox2-2/+2
targets PR 30923 * testsuite/ld-arm/thumb-plt-got.d: Skip test for configurations using the MUSL library. * testsuite/ld-arm/thumb-plt.d: Likewise.
2023-10-05Fix: ld testsuite: pr22001-1 test segfaults on musl/x86A. Wilcox1-10/+16
PR 30925 PR 22001 * testsuite/ld-i386/i386.exp: Skip the pr22001 test with TEXTREL relocations enabled on configurations using the MUSL library.
2023-10-05Fix: ld testsuite: 'Version' pattern grabs 'Version5 EABI', breaking test on ↵A. Wilcox1-2/+4
arm-linux-musleabihf PR 30924 * testsuite/ld-elfvers/vers.exp (objdump_emptyverstuff): Handle EABI version information in objdump's output.
2023-09-29x86-64: Add -z mark-plt and -z nomark-pltH.J. Lu10-0/+127
The PLT entry in executables and shared libraries contains an indirect branch, like jmp *foo@GOTPCREL(%rip) push $index_foo jmp .PLT0 or endbr64 jmp *foo@GOTPCREL(%rip) NOP padding which is used to branch to the function, foo, defined in another object. Each R_X86_64_JUMP_SLOT relocation has a corresponding PLT entry. The dynamic tags have been added to the x86-64 psABI to mark such PLT entries: https://gitlab.com/x86-psABIs/x86-64-ABI/-/commit/6d824a52a42d173eb838b879616c1be5870b593e Add an x86-64 linker option, -z mark-plt, to mark PLT entries with #define DT_X86_64_PLT (DT_LOPROC + 0) #define DT_X86_64_PLTSZ (DT_LOPROC + 1) #define DT_X86_64_PLTENT (DT_LOPROC + 3) 1. DT_X86_64_PLT: The address of the procedure linkage table. 2. DT_X86_64_PLTSZ: The total size, in bytes, of the procedure linkage table. 3. DT_X86_64_PLTENT: The size, in bytes, of a procedure linkage table entry. and set the r_addend field of the R_X86_64_JUMP_SLOT relocation to the memory offset of the indirect branch instruction. The dynamic linker can use these tags to update the PLT section to direct branch. bfd/ * elf-linker-x86.h (elf_linker_x86_params): Add mark_plt. * elf64-x86-64.c (elf_x86_64_finish_dynamic_symbol): Set the r_addend of R_X86_64_JUMP_SLOT to the indirect branch offset in PLT entry for -z mark-plt. * elfxx-x86.c (_bfd_x86_elf_size_dynamic_sections): Add DT_X86_64_PLT, DT_X86_64_PLTSZ and DT_X86_64_PLTENT for -z mark-plt. (_bfd_x86_elf_finish_dynamic_sections): Set DT_X86_64_PLT, DT_X86_64_PLTSZ and DT_X86_64_PLTENT. (_bfd_x86_elf_get_synthetic_symtab): Ignore addend for JUMP_SLOT relocation. (_bfd_x86_elf_link_setup_gnu_properties): Set plt_indirect_branch_offset. * elfxx-x86.h (elf_x86_plt_layout): Add plt_indirect_branch_offset. binutils/ * readelf.c (get_x86_64_dynamic_type): New function. (get_dynamic_type): Call get_x86_64_dynamic_type. include/ * elf/x86-64.h (DT_X86_64_PLT): New. (DT_X86_64_PLTSZ): Likewise. (DT_X86_64_PLTENT): Likewise. ld/ * ld.texi: Document -z mark-plt and -z nomark-plt. * emulparams/elf32_x86_64.sh: Source x86-64-plt.sh. * emulparams/elf_x86_64.sh: Likewise. * emulparams/x86-64-plt.sh: New file. * testsuite/ld-x86-64/mark-plt-1.s: Likewise. * testsuite/ld-x86-64/mark-plt-1a-x32.d: Likewise. * testsuite/ld-x86-64/mark-plt-1a.d: Likewise. * testsuite/ld-x86-64/mark-plt-1b-x32.d: Likewise. * testsuite/ld-x86-64/mark-plt-1b.d: Likewise. * testsuite/ld-x86-64/mark-plt-1c-x32.d: Likewise. * testsuite/ld-x86-64/mark-plt-1c.d: Likewise. * testsuite/ld-x86-64/mark-plt-1d-x32.d: Likewise. * testsuite/ld-x86-64/mark-plt-1d.d: Likewise. * testsuite/ld-x86-64/x86-64.exp: Run -z mark-plt tests.
2023-09-25Revert "arc: Add new LD tests for ARCv3."Claudiu Zissulescu11-183/+0
This reverts commit 6e467e9a94c1135bd11d985e9263d43204a9258b.
2023-09-25Revert "arc: Add new linker emulation and scripts for ARCv3 ISA."Claudiu Zissulescu2-0/+19
This reverts commit 4deb1ee57fdb711cac6f36fed75b3c8cb5112d99.
2023-09-25RISC-V: Protect .got with relroAndreas Schwab1-1/+0
Move .got before .data so that it can be protected with -zrelro. Also separate .got.plt from .got if -znow is not in effect; the first two words of .got.plt are placed within the relro region. ld: PR ld/30877 * emulparams/elf32lriscv-defs.sh (DATA_GOT, SEPARATE_GOTPLT): Define. * emulparams/elf64lriscv-defs.sh (SEPARATE_GOTPLT): Define. * testsuite/ld-elf/binutils.exp (binutils_test): Remove riscv*-*-* from relro_got expression.
2023-09-25arc: Add new linker emulation and scripts for ARCv3 ISA.Claudiu Zissulescu2-19/+0
Add ARCv3's linker bits. Remove obsolete tests. ld/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * ld/Makefile.am: Add ARC64 targets. * ld/configure.tgt: Likewise. * ld/Makefile.in: Regenerate. * ld/emulparams/arc64elf32.sh: New file. * ld/emulparams/arc64elf64.sh: Likewise. * ld/emulparams/arc64linux32.sh: Likewise. * ld/emulparams/arc64linux64.sh: Likewise. * ld/scripttempl/elfarc.sc: Update stack and heap definitions. * ld/testsuite/ld-arc/got-weak.d: Deleted file. * ld/testsuite/ld-arc/got-weak.s: Likewise. Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2023-09-25arc: Add new LD tests for ARCv3.Claudiu Zissulescu11-0/+183
Add new linker tests for ARCv3 ISA. All the new tests are added in a distinct new folder named arc64. ld/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * ld/testsuite/ld-arc64/arcv3_64-reloc-near-exe.dd: New file. * ld/testsuite/ld-arc64/arcv3_64-reloc-near-so.dd: Likewise. * ld/testsuite/ld-arc64/arcv3_64-reloc-near.s: Likewise. * ld/testsuite/ld-arc64/arcv3_64.exp: Likewise. * ld/testsuite/ld-arc64/bl34.dd: Likewise. * ld/testsuite/ld-arc64/bl34.s: Likewise. * ld/testsuite/ld-arc64/linkscript.ld: Likewise. * ld/testsuite/ld-arc64/plt34-got.dd: Likewise. * ld/testsuite/ld-arc64/plt34-got.s: Likewise. * ld/testsuite/ld-arc64/plt34-reloc.dd: Likewise. * ld/testsuite/ld-arc64/plt34-reloc.s: Likewise. Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2023-09-04arm: Make 'conflicting CPU architectures' error message more user-friendlyChristophe Lyon2-2/+2
Error messages such as "conflicting CPU architectures 10/16" are not very to understand, so this patch replaces the numbers with the description they actually mean: "conflicting CPU architectures ARM v7E-M vs Pre v4" 2023-09-01 Christophe Lyon <christophe.lyon@linaro.org> bfd/ * elf32-arm.c (tag_cpu_arch_combine): Add name_table parameter and use it. (elf32_arm_merge_eabi_attributes): Update call to tag_cpu_arch_combine. ld/ * testsuite/ld-arm/attr-merge-9.out: Update expected error message. * testsuite/ld-arm/attr-merge-arch-2.d: Likewise.
2023-09-01RISC-V: move various alias entriesJan Beulich7-10/+10
For disassembly to only use spec-mandated aliases, respective non-alias entries need to come ahead of their alias ones. Since identical mnemonics need to stay together, whole groups are moved up where necessary. This partly reverts 839189bc932e ("RISC-V: re-arrange opcode table for consistent alias handling"), but then also goes beyond a plain revert. Reviewed-by: Tsukasa OI <research_trasio@irq.a4lg.com> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-08-31elf: Adjust PR ld/30791 testsH.J. Lu2-0/+7
Adjust PR ld/30791 tests: 1. Generic linker targets don't comply with all orhpan section merging rules. 2. z80 fails since a, b, c, d are registers for z80. 3. hppa fails since .text sections aren't merged for relocatable link. PR ld/30791 * testsuite/ld-elf/pr30791a.d: Xfail for generic and z80 targets. * testsuite/ld-elf/pr30791b.d: Xfail for hppa and z80 targets.
2023-08-30elf: Don't merge sections with different SHF_LINK_ORDERH.J. Lu6-0/+107
For relocatable link, don't merge 2 SHF_LINK_ORDER sections if output sections of their linked to sections are different. * ldelf.c (elf_orphan_compatible): Don't merge sections with different SHF_LINK_ORDER. * testsuite/ld-elf/pr30791a.d: New file. * testsuite/ld-elf/pr30791a.s: Likewise. * testsuite/ld-elf/pr30791b.d: Likewise. * testsuite/ld-elf/pr30791b.s: Likewise. * testsuite/ld-elf/pr30791c.s: Likewise. * testsuite/ld-elf/pr30791d.s: Likewise.
2023-08-23x86: Fix DT_JMPREL/DT_PLTRELSZ when relocs share a sectionPeter Edwards8-0/+36
If a linker script does not place the PLT relocations and "normal" relocations in separate ELF sections, `ld` will currently output incorrect values for DT_JMPREL and DT_PLTRELSZ - they cover the entire ELF section, rather than just the PLT relocations Don't ignore the extent of the BFD section - use the size of the srelplt BFD section and its offset from the output_secttion bfd/ PR ld/30787 * elfxx-x86.c (_bfd_x86_elf_finish_dynamic_sections): Use input section for DT_JMPREL and DT_PLTRELSZ. ld/ PR ld/30787 * testsuite/ld-i386/i386.exp: Run pr30787. * testsuite/ld-x86-64/x86-64.exp: Likewise. * testsuite/ld-i386/pr30787.d: New file. * testsuite/ld-i386/pr30787.s: Likewise. * testsuite/ld-i386/pr30787.t: Likewise. * testsuite/ld-x86-64/pr30787.d: Likewise. * testsuite/ld-x86-64/pr30787.s: Likewise. * testsuite/ld-x86-64/pr30787.t: Likewise.
2023-08-17ld: ld-lib.exp: log failed dump.out contents for debuggingSam James1-2/+2
If we're using dump_prog in a test which fails, log the dump.out contents to ld.log to aid debugging. This avoids needing to ask reporters to manually run e.g. `objdump` commands when making bug reports. PR30722 * ld/testsuite/lib/ld-lib.exp: Log failed dump.out contents to aid debugging. Approved-by: Nick Clifton <nickc@redhat.com> Signed-off-by: Sam James <sam@gentoo.org>
2023-08-16kvx: New port.Paul Iannetta40-2/+877
2023-08-14ld: Build libpr23169a.so with -z lazyH.J. Lu1-2/+2
pr23169b test only works with lazy binding. To work with linker which disables lazy binding by default, build pr23169b binaries with -z lazy. PR ld/30698 * ld-ifunc/ifunc.exp: Build pr23169b binaries with -z lazy.
2023-08-14ld: fix relocatable, retain7a target pattens for HPPASam James2-2/+2
Fix issue reported by Dave and Alan. Put back the old pattern for hppa-*-linux* and add hppa[12]*-*-linux* to cover Gentoo's hppa1.1 and hppa2.0 without including hppa64 inadvertently like I did before. ld/ PR 30733 PR 30734 * ld/testsuite/ld-elf/relocatable.d: Use better pattern to exclude hppa64 but include hppa1.1, hppa2.0. * ld/testsuite/ld-elf/retain7a.d: Ditto. Fixes: 0e339f6b4f2df25ed351cb94dc7fe16868626f49 Fixes: e3b66187192ce6840df283c00f6395bb0ff15cf5 Signed-off-by: Sam James <sam@gentoo.org>
2023-08-08ld: Fix retain7a.d XFAIL/notarget entry for hppaSam James1-1/+1
PR 30733 * ld/testsuite/ld-elf/retain7a.d: Fix XFAIL entry for hppa to match hppa{1.1,2.0}*, like hppa2.0-unknown-linux-gnu which Gentoo uses. Signed-off-by: Sam James <sam@gentoo.org>
2023-08-08ld: Fix relocatable.d XFAIL/notarget entry for hppaSam James1-1/+1
PR 30734 * ld/testsuite/ld-elf/relocatable.d: Fix notarget entry for hppa to match hppa{1.1,2.0}*, like hppa2.0-unknown-linux-gnu which Gentoo uses. Signed-off-by: Sam James <sam@gentoo.org>
2023-08-04PR30697, ppc32 mix of local-dynamic and global-dynamic TLSAlan Modra3-0/+30
This fixes miscounting of dynamic relocations on GOT entries when a) there are both local-dynamic and global-dynamic tls accesss for a given symbol, and b) the symbol is global with non-default visibility, and c) the __tls_get_addr calls aren't optimised away. PR 30697 bfd/ * elf32-ppc.c (allocate_dynrelocs): Correct local-dynamic reloc count. ld/ * testsuite/ld-powerpc/tls32ldgd.d, * testsuite/ld-powerpc/tls32ldgd.s: New test. * testsuite/ld-powerpc/powerpc.exp: Run it.
2023-08-02Revert "2.41 Release sources"Sam James55-55/+58
This reverts commit 675b9d612cc59446e84e2c6d89b45500cb603a8d. See https://sourceware.org/pipermail/binutils/2023-August/128761.html.
2023-08-022.41 Release sourcesbinutils-2_41-releaseNick Clifton55-58/+55
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