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2016-03-07[AArch64] Create .got section if _GLOBAL_OFFSET_TABLE_ referencedJiong Wang3-0/+9
2016-03-07 Jiong Wang <jiong.wang@arm.com> bfd/ * elfnn-aarch64.c (elfNN_aarch64_check_relocs): Always create .got section if the symbol "_GLOBAL_OFFSET_TABLE_" referenced. ld/ * testsuite/ld-aarch64/implicit_got_section_1.s: New test source file. * testsuite/ld-aarch64/implicit_got_section_1.d: New test expected result. * testsuite/ld-aarch64/aarch64-elf.exp: Run new test.
2016-02-26[BFD][AARCH64]Fix MOVW_SABS_G(0,1,2) relocation overflow check.Renlin Li10-26/+58
For these three relocations, 17 bit signed value should be used, instead of 16 bit. The bitsize field is changed from 16 to 17, this field in aarch64 backend is used for overflow check only. bfd/ 2016-02-26 Renlin Li <renlin.li@arm.com> * elfnn-aarch64.c (elfNN_aarch64_howto_table): Fix signed overflow check for MOVW_SABS_G0, MOVW_SABS_G1, MOVW_SABS_G2. ld/ 2016-02-26 Renlin Li <renlin.li@arm.com> * testsuite/ld-aarch64/aarch64-elf.exp: Run new testcases. * testsuite/ld-aarch64/emit-relocs-270.d: Update to use new boundary. * testsuite/ld-aarch64/emit-relocs-271.d: Likewise. * testsuite/ld-aarch64/emit-relocs-272.d: Likewise. * testsuite/ld-aarch64/emit-relocs-270-overflow.d: New. * testsuite/ld-aarch64/emit-relocs-270-overflow.s: New. * testsuite/ld-aarch64/emit-relocs-271-overflow.d: New. * testsuite/ld-aarch64/emit-relocs-271-overflow.s: New. * testsuite/ld-aarch64/emit-relocs-272-overflow.d: New. * testsuite/ld-aarch64/emit-relocs-272-overflow.s: New.
2016-02-24Revert "ABS32"Renlin Li3-17/+0
This reverts commit 30bdf5c82e5734ac9f0b18eb7af631806d419270.
2016-02-24ABS32Renlin Li3-0/+17
2016-02-09Add a more helpful warning message to explain why some AArch64 relocations ↵Nick Clifton4-2/+27
can overflow. bfd * elfnn-aarch64.c (elfNN_aarch64_relocate_section): Add a more helpful warning message to explain why certain AArch64 relocs might overflow. ld * testsuite/ld-aarch64/reloc-overflow-bad.d: New test. * testsuite/ld-aarch64/reloc-overflow-1.s: New source file. * testsuite/ld-aarch64/reloc-overflow-2.s: New source file. * testsuite/ld-aarch64/aarch64-elf.exp: Run the new test.
2016-02-09Revert "Add a more helpful warning message to explain why some AArch64 ↵Walfred Tedeschi4-27/+2
relocations can overflow." This reverts commit 2ea53e003163338a403d5afbb2046cafb8f3abe9.
2016-02-09Add a more helpful warning message to explain why some AArch64 relocations ↵Nick Clifton4-2/+27
can overflow. bfd * elfnn-aarch64.c (elfNN_aarch64_relocate_section): Add a more helpful warning message to explain why certain AArch64 relocs might overflow. ld * testsuite/ld-aarch64/reloc-overflow-bad.d: New test. * testsuite/ld-aarch64/reloc-overflow-1.s: New source file. * testsuite/ld-aarch64/reloc-overflow-2.s: New source file. * testsuite/ld-aarch64/aarch64-elf.exp: Run the new test.
2016-01-21[AArch64] Relax long branch veneer insertion for non STT_FUNC symbolJiong Wang9-27/+150
As defined at AArch64 ELF Specification (4.6.7 Call and Jump relocations), symbol with type of non STT_FUNC but in different input section with relocation place should insert long branch veneer also. Meanwhile the current long branch veneer infrastructure havn't considered the situation where the branch destination is "sym_value + rela->addend". This was OK because we only insert veneer for long call destination is STT_FUNC symbol for which the addend is always zero. But as we relax the support to other situations by this patch, we need to handle addend be non-zero value. For example, for static function, relocation against "local symbol" are turned into relocation against "section symbol + offset" where there is a valid addend. bfd/ * elfnn-aarch64.c (aarch64_type_of_stub): Allow insert long branch veneer for sym_sec != input_sec. (elfNN_aarch64_size_stub): Support STT_SECTION symbol. (elfNN_aarch64_final_link_relocate): Take rela addend into account when calculation destination. ld/ * testsuite/ld-aarch64/farcall-section.d: Delete. * testsuite/ld-aarch64/farcall-section.s: Delete. * testsuite/ld-aarch64/farcall-b-section.d: New expectation file. * testsuite/ld-aarch64/farcall-bl-section.d: Likewise. * testsuite/ld-aarch64/farcall-b-section.s: New testcase. * testsuite/ld-aarch64/farcall-bl-section.s: Likewise. * testsuite/ld-aarch64/aarch64-elf.exp: Likewise.
2016-01-01Copyright update for binutilsAlan Modra1-1/+1
2015-11-12Revert "[LD][AARCH64]Add TLSIE relaxation support under large memory model."Marcus Shawcroft3-34/+0
This reverts commit 3ebe65c0ff9f8f76c9971b1cc078273298f0c693. Reverted due to PR19188
2015-11-03[LD][AARCH64]Add test cases for big-endian.Renlin Li23-0/+290
ld/testsuite 2015-11-03 Renlin Li <renlin.li@arm.com> * ld-aarch64/aarch64-elf.exp: Run newly added test cases. * ld-aarch64/emit-relocs-301.d: Skip aarch64_be. * ld-aarch64/emit-relocs-302.d: Likwise. * ld-aarch64/emit-relocs-310.d: Likwise. * ld-aarch64/emit-relocs-515.d: Likwise. * ld-aarch64/emit-relocs-516.d: Likwise. * ld-aarch64/tls-large-desc.d: Likwise. * ld-aarch64/tls-large-ie.d: Likwise. * ld-aarch64/tls-relax-large-desc-ie.d: Likwise. * ld-aarch64/tls-relax-large-desc-le.d: Likwise. * ld-aarch64/tls-relax-large-gd-ie.d: Likwise. * ld-aarch64/tls-relax-large-gd-le.d: Likwise. * ld-aarch64/emit-relocs-301-be.d: New for aarch64_be. * ld-aarch64/emit-relocs-302-be.d: Likewise. * ld-aarch64/emit-relocs-310-be.d: Likewise. * ld-aarch64/emit-relocs-515-be.d: Likewise. * ld-aarch64/emit-relocs-516-be.d: Likewise. * ld-aarch64/tls-large-desc-be.d: Likewise. * ld-aarch64/tls-large-ie-be.d: Likewise. * ld-aarch64/tls-relax-large-desc-ie-be.d: Likewise. * ld-aarch64/tls-relax-large-desc-le-be.d: Likewise. * ld-aarch64/tls-relax-large-gd-ie-be.d: Likewise. * ld-aarch64/tls-relax-large-gd-le-be.d: Likewise.
2015-10-02[LD][AARCH64]Add TLSIE relaxation support under large memory model.Renlin Li3-0/+34
bfd/ 2015-10-02 Renlin Li <renlin.li@arm.com> * elfnn-aarch64.c (IS_AARCH64_TLS_RELAX_RELOC): Add TLSIE_MOVW_GOTTPREL_G1. (aarch64_tls_transition_without_check): Add TLSIE_MOVW_GOTTPREL_G1 to TLSLE_MOVW_TPREL_G2 transition for local symbol. (elfNN_aarch64_tls_relax): Add a argument to pass tp offset. Add TLSIE_MOVW_GOTTPREL_G1 relaxation. (elfNN_aarch64_relocate_section): Call elfNN_aarch64_tls_relax with new argument. ld/testsuite/ 2015-10-02 Renlin Li <renlin.li@arm.com> * ld-aarch64/aarch64-elf.exp (tls-relax-large-le-ie): Run new test. * ld-aarch64/tls-relax-large-ie-le.d: New. * ld-aarch64/tls-relax-large-ie-le.s: New.
2015-10-02[LD][AARCH64]Add TLSDESC support for large memory model.Renlin Li7-0/+135
bfd/ 2015-10-02 Renlin Li <renlin.li@arm.com> * elfnn-aarch64.c (aarch64_tls_transition_without_check): Add relax transitions for TLSDESC_ADD, TLSDESC_LDR, TLSDESC_OFF_G0_NC, TLSDESC_OFF_G1. (aarch64_tls_transition_without_check): Add relaxation support. (aarch64_reloc_got_type): Add support. (elfNN_aarch64_final_link_relocate): Likewise. (elfNN_aarch64_tls_relax): Likewise. (elfNN_aarch64_relocate_section): Likewise. (elfNN_aarch64_gc_sweep_hook): Likewise. (elfNN_aarch64_check_relocs): Likewise. * elfxx-aarch64.c (_bfd_aarch64_elf_put_addend): Likewise. (_bfd_aarch64_elf_resolve_relocation): Likewise. ld/testsuite/ 2015-10-02 Renlin Li <renlin.li@arm.com> * ld-aarch64/aarch64-elf.exp: Run new test. * ld-aarch64/tls-large-desc.d: New. * ld-aarch64/tls-large-desc.s: New. * ld-aarch64/tls-relax-large-desc-ie.d: New. * ld-aarch64/tls-relax-large-desc-ie.s: New. * ld-aarch64/tls-relax-large-desc-le.d: New. * ld-aarch64/tls-relax-large-desc-le.s: New.
2015-10-02[BFD][AARCH64]Add TLSGD relaxation support under large memory model.Renlin Li5-0/+73
bfd/ 2015-10-02 Renlin Li <renlin.li@arm.com> * elfnn-aarch64.c(IS_AARCH64_TLS_RELAX_RELOC): Add relaxation support for TLSGD_MOVW_G0_NC and TLSGD_MOVW_G1. (aarch64_tls_transition_without_check): Likewise (elfNN_aarch64_tls_relax): Likwise. ld/testsuite/ 2015-10-02 Renlin Li <renlin.li@arm.com> * ld-aarch64/aarch64-elf.exp: run new test * ld-aarch64/tls-relax-large-gd-ie.d: New. * ld-aarch64/tls-relax-large-gd-ie.s: New. * ld-aarch64/tls-relax-large-gd-le.d: New. * ld-aarch64/tls-relax-large-gd-le.s: New.
2015-10-02[Binutils][AARCH64]Add TLS IE large memory support.Renlin Li3-0/+35
bfd/ 2015-10-02 Renlin Li <renlin.li@arm.com> * reloc.c: Make AARCH64_TLSIE_MOVW_GOTTPREL_G1 and AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC defined in alphabetical order. * libbfd.h: Regenerate. * bfd-in2.h: Likewise. * elfnn-aarch64.c (elfNN_aarch64_howto_table): Make TLSIE_MOVW_GOTTPREL_G1 check overflow. (aarch64_reloc_got_type): Add support for TLSIE_MOVW_GOTTPREL_G1 and TLSIE_MOVW_GOTTPREL_G0_NC. (elfNN_aarch64_final_link_relocate): Likewise. (elfNN_aarch64_relocate_section): Likewise. (elfNN_aarch64_gc_sweep_hook): Likewise. (elfNN_aarch64_check_relocs): Likewise. * elfxx-aarch64.c (_bfd_aarch64_elf_put_addend): Likewise. (_bfd_aarch64_elf_resolve_relocation): Likewise. gas/ 2015-10-02 Renlin Li <renlin.li@arm.com> * config/tc-aarch64.c (reloc_table): Add two entries for gottprel_g0_nc and gottprel_g1. (process_movw_reloc_info): Add support. (md_apply_fix): Likewise. (aarch64_force_relocation): Likewise. gas/testsuite/ 2015-10-02 Renlin Li <renlin.li@arm.com> * gas/aarch64/reloc-gottprel_g0_nc.d: New. * gas/aarch64/reloc-gottprel_g0_nc.s: New. * gas/aarch64/reloc-gottprel_g1.d: New. * gas/aarch64/reloc-gottprel_g1.s: New. ld/testsuite/ 2015-10-02 Renlin Li <renlin.li@arm.com> * ld-aarch64/tls-large-ie.d: New. * ld-aarch64/tls-large-ie.s: New. * ld-aarch64/aarch64-elf.exp: Run new test.
2015-10-02[LD][AARCH64]Add BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC support.Renlin Li3-0/+50
bfd/ 2015-10-02 Renlin Li <renlin.li@arm.com> * elfnn-aarch64.c (aarch64_reloc_got_type): Add BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC support. (elfNN_aarch64_final_link_relocate): Likewise. (elfNN_aarch64_relocate_section): Likewise. (elfNN_aarch64_gc_sweep_hook): Likewise. (elfNN_aarch64_check_relocs): Likewise. * elfxx-aarch64.c (_bfd_aarch64_elf_put_addend): Likewise. (_bfd_aarch64_elf_resolve_relocation): Likewise. ld/testsuite/ 2015-10-02 Renlin Li <renlin.li@arm.com> * ld-aarch64/emit-relocs-516.d: New. * ld-aarch64/emit-relocs-516.s: New. * ld-aarch64/aarch64-elf.exp: Run new test.
2015-10-02[LD][AARCH64]Add BFD_RELOC_AARCH64_TLSGD_MOVW_G1 support.Renlin Li3-0/+47
bfd/ 2015-10-02 Renlin Li <renlin.li@arm.com> * elfnn-aarch64.c (aarch64_reloc_got_type): Add BFD_RELOC_AARCH64_TLSGD_MOVW_G1 support. (elfNN_aarch64_final_link_relocate): Likewise. (elfNN_aarch64_relocate_section): Likewise. (elfNN_aarch64_gc_sweep_hook): Likewise. (elfNN_aarch64_check_relocs): Likewise. * elfxx-aarch64.c (_bfd_aarch64_elf_put_addend): Likewise. (_bfd_aarch64_elf_resolve_relocation): Likewise. ld/testsuite 2015-10-02 Renlin Li <renlin.li@arm.com> * ld-aarch64/emit-relocs-515.d: New. * ld-aarch64/emit-relocs-515.s: New. * ld-aarch64/aarch64-elf.exp: Run new test.
2015-10-02[LD][AARCH64]Add BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC Support.Renlin Li3-1/+36
bfd/ 2015-10-02 Renlin Li <renlin.li@arm.com> * elfnn-aarch64.c (aarch64_reloc_got_type): Add BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC support. (elfNN_aarch64_final_link_relocate): Likewise. (elfNN_aarch64_gc_sweep_hook): Likewise. (elfNN_aarch64_check_relocs): Likewise. * elfxx-aarch64.c (_bfd_aarch64_elf_put_addend): Likewise. (_bfd_aarch64_elf_resolve_relocation): Likewise. ld/testsuite/ 2015-10-02 Renlin Li <renlin.li@arm.com> * ld-aarch64/aarch64-elf.exp: Run new test. * ld-aarch64/emit-relocs-301.d: New. * ld-aarch64/emit-relocs-301.s: New.
2015-10-02[LD][AARCH64]Add BFD_RELOC_AARCH64_MOVW_GOTOFF_G1 Support.Renlin Li3-1/+37
bfd/ 2015-10-02 Renlin Li <renlin.li@arm.com> * elfnn-aarch64.c (aarch64_reloc_got_type): Add support for BFD_RELOC_AARCH64_MOVW_GOTOFF_G1. (elfNN_aarch64_gc_sweep_hook): Likewise. (elfNN_aarch64_check_relocs): Likewise * elfxx-aarch64.c (_bfd_aarch64_elf_put_addend): Likewise. (_bfd_aarch64_elf_resolve_relocation): Likewise (elfNN_aarch64_final_link_relocate): Calculate offset within GOT. ld/testsuite/ 2015-10-02 Renlin Li <renlin.li@arm.com> * ld-aarch64/emit-relocs-302.d: New. * ld-aarch64/emit-relocs-302.s: New. * ld-aarch64/aarch64-elf.exp: Run the new test.
2015-10-02[LD][AARCH64]Add BFD_RELOC_AARCH64_LD64_GOTOFF_LO15 Support.Renlin Li3-1/+33
bfd/ 2015-10-02 Renlin Li <renlin.li@arm.com> * elfnn-aarch64.c (aarch64_reloc_got_type): Add BFD_RELOC_AARCH64_LD_64_GOTOFF_LO15 support. (elfNN_aarch64_gc_sweep_hook): Likewise. (elfNN_aarch64_check_relocs): Likewise * elfxx-aarch64.c (_bfd_aarch64_elf_put_addend): Likewise. (_bfd_aarch64_elf_resolve_relocation): Likewise (elfNN_aarch64_final_link_relocate): Calculate offset within GOT. ld/testsuite/ 2015-10-02 Renlin Li <renlin.li@arm.com> * ld-aarch64/emit-relocs-310.d: New. * ld-aarch64/emit-relocs-310.s: New. * ld-aarch64/aarch64-elf.exp: Run the test.
2015-10-01[BFD][AARCH64]Emit single AARCH64_MAP_INSN symbol for the whole plt.Renlin Li3-0/+18
bfd/ 2015-10-01 Renlin Li <renlin.li@arm.com> * elfnn-aarch64.c (elfNN_aarch64_output_plt_map): Remove. (elfNN_aarch64_output_arch_local_syms): Emit AARCH64_MAP_INSN once. ld/testsuite/ 2015-10-01 Renlin Li <renlin.li@arm.com> * ld-aarch64/plt_mapping_symbol.d: New. * ld-aarch64/plt_mapping_symbol.s: New. * ld-aarch64/aarch64-elf.exp: Run the new test.
2015-09-09[AArch64] Relax TLS local dynamic traditional into local executableJiong Wang5-0/+80
The linker relaxation logic will be: Code sequence I (tiny): 0x00 adr x0, :tlsldm:x 0x04 bl __tls_get_addr | V 0x00 mrs x0, tpidr_el0 0x04 add x0, x0, TCB_SIZE Code sequence II (small): 0x00 adrp a0, :tlsldm:x 0x04 add a0, #:tlsldm_lo12:x 0x08 bl __tls_get_addr | V 0x00 mrs x0, tpidr_el0 0x04 add x0, x0, TCB_SIZE 0x08 nop 2015-09-09 Jiong Wang <jiong.wang@arm.com> bfd/ * elfnn-aarch64.c (aarch64_tls_transition_without_check): Support three TLS local dynamic traditional relocations types. (elfNN_aarch64_tls_relax): Support TLS local dynamic traditional to local executable relaxation. ld/testsuite/ * ld-aarch64/tls-relax-ld-le-tiny.s: New testcase. * ld-aarch64/tls-relax-ld-le-small.s: Likewise. * ld-aarch64/tls-relax-ld-le-tiny.d: New expectation file. * ld-aarch64/tls-relax-ld-le-small.d: Likewise. * ld-aarch64/aarch64-elf.exp: Run new testcases.
2015-08-19[AArch64][6/6] LD support TLSLD load/store relocation typesJiong Wang25-0/+248
2015-08-19 Jiong Wang <jiong.wang@arm.com> bfd/ * elfnn-aarch64.c (IS_AARCH64_TLS_RELOC): Recognize new relocation types, including BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12, BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC, BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12, BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC, BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12, BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC, BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12, BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC. (elfNN_aarch64_final_link_relocate): Likewise. * elfxx-aarch64.c (_bfd_aarch64_elf_put_addend): Likewise. (_bfd_aarch64_elf_resolve_relocation): Likewise. ld/testsuite/ * ld-aarch64/emit-relocs-531.s: New testcase. * ld-aarch64/emit-relocs-531-overflow.s: Likewise. * ld-aarch64/emit-relocs-532.s: Likewise. * ld-aarch64/emit-relocs-533.s: Likewise. * ld-aarch64/emit-relocs-533-overflow.s: Likewise. * ld-aarch64/emit-relocs-534.s: Likewise. * ld-aarch64/emit-relocs-535.s: Likewise. * ld-aarch64/emit-relocs-535-overflow.s: Likewise. * ld-aarch64/emit-relocs-536.s: Likewise. * ld-aarch64/emit-relocs-537.s: Likewise. * ld-aarch64/emit-relocs-537-overflow.s: Likewise. * ld-aarch64/emit-relocs-538.s: Likewise. * ld-aarch64/emit-relocs-531.d: New expectation file. * ld-aarch64/emit-relocs-531-overflow.d: Likewise. * ld-aarch64/emit-relocs-532.d: Likewise. * ld-aarch64/emit-relocs-533.d: Likewise. * ld-aarch64/emit-relocs-533-overflow.d: Likewise. * ld-aarch64/emit-relocs-534.d: Likewise. * ld-aarch64/emit-relocs-535.d: Likewise. * ld-aarch64/emit-relocs-535-overflow.d: Likewise. * ld-aarch64/emit-relocs-536.d: Likewise. * ld-aarch64/emit-relocs-537.d: Likewise. * ld-aarch64/emit-relocs-537-overflow.d: Likewise. * ld-aarch64/emit-relocs-538.d: Likewise. * ld-aarch64/aarch64-elf.exp: Run new testcases.
2015-08-19[AArch64][4/6] LD support TLSLD move/add relocation typesJiong Wang29-0/+253
2015-08-19 Jiong Wang <jiong.wang@arm.com> bfd/ PR ld/18276 * elfnn-aarch64.c (IS_AARCH64_TLS_RELOC): Recognize new relocation types, including BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12, BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0, BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC, BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1, BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC, BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2. (elfNN_aarch64_final_link_relocate): Likewise. * elfxx-aarch64.c (_bfd_aarch64_elf_put_addend): Likewise. (_bfd_aarch64_elf_resolve_relocation): Likewise. ld/testsuite/ * ld-aarch64/emit-relocs-87.s: New testcase. * ld-aarch64/emit-relocs-88.s: Likewise. * ld-aarch64/emit-relocs-88-overflow.s: Likewise. * ld-aarch64/emit-relocs-89.s: Likewise. * ld-aarch64/emit-relocs-90.s: Likewise. * ld-aarch64/emit-relocs-90-overflow.s: Likewise. * ld-aarch64/emit-relocs-523.s: Likewise. * ld-aarch64/emit-relocs-524.s: Likewise. * ld-aarch64/emit-relocs-525.s: Likewise. * ld-aarch64/emit-relocs-527.s: Likewise. * ld-aarch64/emit-relocs-526.s: Likewise. * ld-aarch64/emit-relocs-528.s: Likewise. * ld-aarch64/emit-relocs-528-overflow.s: Likewise. * ld-aarch64/emit-relocs-87.d: New expectation file. * ld-aarch64/emit-relocs-88.d: Likewise. * ld-aarch64/emit-relocs-88-overflow.d: Likewise. * ld-aarch64/emit-relocs-89.d: Likewise. * ld-aarch64/emit-relocs-90.d: Likewise. * ld-aarch64/emit-relocs-90-overflow.d: Likewise. * ld-aarch64/emit-relocs-91.d: Likewise. * ld-aarch64/emit-relocs-523.d: Likewise. * ld-aarch64/emit-relocs-524.d: Likewise. * ld-aarch64/emit-relocs-525.d: Likewise. * ld-aarch64/emit-relocs-526.d: Likewise. * ld-aarch64/emit-relocs-527.d: Likewise. * ld-aarch64/emit-relocs-528.d: Likewise. * ld-aarch64/emit-relocs-528-overflow.d: Likewise. * ld-aarch64/aarch64-elf.exp: Run new testcases.
2015-08-19[AArch64][2/6] LD support BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NCJiong Wang5-0/+37
2015-08-19 Jiong Wang <jiong.wang@arm.com> bfd/ * elfnn-aarch64.c (IS_AARCH64_TLS_RELOC): Recognize BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC. (aarch64_reloc_got_type): Likewise. (elfNN_aarch64_final_link_relocate): Likewise. (elfNN_aarch64_relocate_section): Likewise. * elfxx-aarch64.c (_bfd_aarch64_elf_put_addend): Likewise. (_bfd_aarch64_elf_resolve_relocation): Likewise. ld/testsuite/ * ld-aarch64/emit-relocs-530.s: New testcase. * ld-aarch64/emit-relocs-92.s: Likewise. * ld-aarch64/emit-relocs-530.d: New expectation file. * ld-aarch64/emit-relocs-92.d: Likewise. * ld-aarch64/aarch64-elf.exp: Run new testcases.
2015-08-12[AArch64] Fix test failures on elf configurationJiong Wang5-29/+36
This patch fixed those failures on elf configuration by: * Improve the ILP32 target selector "aarch64_choose_ilp32_emul", makes it more robust. Target triples copied from configure.tgt * Updated emit-relocs-86/-overflow.d to use aarch64_choose_ilp32_emul which is following what have done with emit-relocs-28. * Those instruction encoding mismatch is because those encoding contains pc-relative address. As for elf, we may have different start address. relaxed encodind check, especially for aarch64-farcall-b/bl-plt, as the main purpose of those check are ELF text/data layout, we just want to make sure veneer to plt stub is generated. 2015-08-12 Jiong Wang <jiong.wang@arm.com> ld/testsuite/ * ld-aarch64/aarch64-elf.exp (aarch64_choose_ilp32_emul): Support all four triple shapes: aarch64-*-linux*, aarch64-*-elf, aarch64_be-*-linux*, aarch64_be-*-elf. * ld-aarch64/emit-relocs-86.d: Use aarch64_choose_ilp32_emul. * ld-aarch64/emit-relocs-86-overflow.d: Likewise. * ld-aarch64/ld-aarch64/farcall-b-plt.d: Relax instrucion encoding check when they reflect address. * ld-aarch64/ld-aarch64/farcall-bl-plt.d: Likewise.
2015-08-12[AArch64] Rename relocs-257-symbolic-func ld test to relocs-1027-symbolic-func.Thomas Preud'homme3-2/+2
2015-08-12 Thomas Preud'homme <thomas.preudhomme@arm.com> ld/testsuite/ * ld-aarch64/aarch64-elf.exp: Rename relocs-257-symbolic-func to relocs-1027-symbolic-func. * ld-aarch64/relocs-257-symbolic-func.d: Rename to ... * ld-aarch64/relocs-1027-symbolic-func.d: ... this. * ld-aarch64/relocs-257-symbolic-func.s: Rename to ... * ld-aarch64/relocs-1027-symbolic-func.s: ... this.
2015-08-11[AArch64] Commit missing testcasesJiong Wang4-0/+56
2015-08-11[AArch64] Long branch veneer support far symbol defined by --defsymJiong Wang1-0/+2
2015-08-11 Jiong Wang <jiong.wang@arm.com> bfd/ * bfd/elfnn-aarch64.c (aarch64_type_of_stub): New parameter "sym_sec". Loose the check for symbol from ABS section. (elfNN_aarch64_size_stubs): Pass sym_sec. ld/testsuite/ * ld-aarch64/farcall-b-defsym.s: New test. * ld-aarch64/farcall-bl-defsym.s: Likewise. * ld-aarch64/farcall-b-defsym.d: New expectation. * ld-aarch64/farcall-bl-defsym.d: Likewise.
2015-08-11[AArch64] PR18668, repair long branch veneer for plt stubJiong Wang7-0/+124
2015-08-11 Jiong Wang <jiong.wang@arm.com> bfd/ PR ld/18668 * elfnn-aarch64.c (aarch64_type_of_stub): Update destination for calls go through plt stub. (elfNN_aarch64_final_link_relocate): Adjust code logic for CALL26, JUMP26 relocation to support inserting veneer for call to plt stub. ld/testsuite/ * ld-aarch64/farcall-b-gsym.s: New test. * ld-aarch64/farcall-b-plt.s: Likewise. * ld-aarch64/farcall-bl-plt.s: Likewise. * ld-aarch64/farcall-b-gsym.d: New expect file. * ld-aarch64/farcall-b-plt.d: Likewise. * ld-aarch64/farcall-bl-plt.d: Likewise.
2015-08-11[AArch64][8/8] LD support BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12Jiong Wang9-0/+70
2015-08-11 Jiong Wang <jiong.wang@arm.com> bfd/ * elfnn-aarch64.c (IS_AARCH64_TLS_RELOC): Recognize BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12. (aarch64_reloc_got_type): Likewise. (elfNN_aarch64_final_link_relocate): Likewise. (elfNN_aarch64_relocate_section): Likewise. * elfxx-aarch64.c (_bfd_aarch64_elf_put_addend): Likewise. (_bfd_aarch64_elf_resolve_relocation): Likewise. ld/testsuite/ * ld-aarch64/emit-relocs-529.s: New testcase. * ld-aarch64/emit-relocs-529-overflow.s: Likewise. * ld-aarch64/emit-relocs-86.s: Likewise. * ld-aarch64/emit-relocs-86-overflow.s: Likewise. * ld-aarch64/emit-relocs-529.d: New expectation file. * ld-aarch64/emit-relocs-529-overflow.d: Likewise. * ld-aarch64/emit-relocs-86.d: Likewise. * ld-aarch64/emit-relocs-86-overflow.d: Likewise. * ld-aarch64/aarch64-elf.exp: Run new testcases.
2015-08-11[AArch64][6/8] LD support BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NCJiong Wang1-1/+2
2015-08-11 Jiong Wang <jiong.wang@arm.com> bfd/ * elfnn-aarch64.c (IS_AARCH64_TLS_RELOC): Recognize BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC. (aarch64_reloc_got_type): Likewise. (elfNN_aarch64_final_link_relocate): Likewise. (elfNN_aarch64_relocate_section): Likewise. (elfNN_aarch64_gc_sweep_hook): Likewise. (elfNN_aarch64_check_relocs): Likewise. * elfxx-aarch64.c (_bfd_aarch64_elf_put_addend): Likewise. (_bfd_aarch64_elf_resolve_relocation): Likewise. ld/testsuite/ * ld-aarch64/tls-small-ld.s: Update testcase.
2015-08-11[AArch64][3/8] LD support BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21Jiong Wang3-0/+17
2015-08-11 Jiong Wang <jiong.wang@arm.com> bfd/ * elfnn-aarch64.c (IS_AARCH64_TLS_RELOC): Recognize BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21. (aarch64_reloc_got_type): Likewise. (elfNN_aarch64_final_link_relocate): Likewise. (elfNN_aarch64_relocate_section): Likewise. (elfNN_aarch64_gc_sweep_hook): Likewise. (elfNN_aarch64_check_relocs): Likewise. * elfxx-aarch64.c (_bfd_aarch64_elf_put_addend): Likewise. (_bfd_aarch64_elf_resolve_relocation): Likewise. ld/testsuite/ * ld-aarch64/tls-small-ld.s: New file. * ld-aarch64/tls-small-ld.d: Likewise. * ld-aarch64/aarch64-elf.exp: Run new test.
2015-07-27[AArch64] Fix extern protected data handlingSzabolcs Nagy3-0/+23
Emit *GLOB_DAT instead of *RELATIVE relocs for protected data in shared objects. This is needed for the fix of glibc bug 17711: https://sourceware.org/bugzilla/show_bug.cgi?id=17711 bfd: PR ld/18705 * elfnn-aarch64.c (elf_backend_extern_protected_data): Define. ld/testsuite: PR ld/18705 * ld-aarch64/protected-data.d: New. * ld-aarch64/protected-data.s: New. * ld-aarch64/aarch64-elf.exp: Add new test.
2015-07-16[AArch64][3/3] LD support BFD_RELOC_AARCH64_TLSLD_ADR_PREL21Jiong Wang3-0/+16
2015-06-23[AArch64] Generate DT_TEXTREL for relocation against read-only sectionJiong Wang3-0/+18
2015-06-23 Jiong Wang <jiong.wang@arm.com> bfd/ * elfnn-aarch64.c (aarch64_readonly_dynrelocs): New function. (elfNN_aarch64_size_dynamic_sections): Traverse hash table to check relocations against read-only sections. ld/testsuite/ * ld-aarch64/dt_textrel.s: New testcase. * ld-aarch64/dt_textrel.d: New expectation file. * ld-aarch64/aarch64-elf.exp: Run new testcase.
2015-06-17[AArch64] Select correct linker emulation for ILP32 according to endianesJiong Wang2-10/+18
2015-06-17 Jiong Wang <jiong.wang@arm.com> ld/testsuite/ * ld-aarch64/aarch64-elf.exp (aarch64_choose_ilp32_emul): New function. * ld-aarch64/emit-relocs-28.d: Use aarch64_choose_ilp32_emul to choose emulation mode.
2015-06-03[AArch64] Revert local changes included in Matthew's commitJiong Wang1-1/+1
When commit the following code for Matthew, I wrongly included my local changes. Revert it. Sorry. commit a5932920ef397c2cbe02efa915686022b78d59a7 Author: Matthew Wahab <matthew.wahab@arm.com> Date: Wed Jun 3 10:03:50 2015 +0100
2015-06-03[ARM] Support for ARMv8.1 command line optionMatthew Wahab1-1/+1
2015-06-03 Matthew Wahab <matthew.wahab@arm.com> gas/ * config/tc-arm.c (arm_archs): Add "armv8.1-a". * doc/c-arm.texi (ARM Options, -march): Add "armv8.1-a". * NEWS: Mention ARMv8.1 support. include/opcode/ * arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New. (ARM_ARCH_V8_1A): New. (ARM_ARCH_V8_1A_FP): New. (ARM_ARCH_V8_1A_SIMD): New. (ARM_ARCH_V8_1A_CRYPTOV1): New. (ARM_FEATURE_CORE): New.
2015-06-02[AArch64] Fix typo in testcaseJiong Wang1-3/+3
ld/testsuite/ * ld-aarch64/emit-relocs-313.s: Use gotpage_lo15.
2015-06-01[AArch64] BFD support BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14Jiong Wang3-0/+25
This patch add BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14 relocation supoprt in bfd linker. 2015-06-01 Jiong Wang <jiong.wang@arm.com> bfd/ * elfnn-aarch64.c (aarch64_reloc_got_type): Support BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14. (elfNN_aarch64_final_link_relocate): Ditto. (elfNN_aarch64_gc_swap_hook): Ditto. (elfNN_aarch64_check_relocs): Ditto. * elfxx-aarch64.c (_bfd_aarch64_elf_put_addend): Ditto. ld/testsuite/ * ld-aarch64/emit-relocs-28.s: New test file. * ld-aarch64/emit-relocs-28.d: Ditto. * ld-aarch64/aarch64-elf.exp: Run new test.
2015-06-01[AArch64] BFD_RELOC_AARCH64_TLSLE_ADD_LO12 should enable overflow checkJiong Wang3-0/+30
BFD_RELOC_AARCH64_TLSLE_ADD_LO12 is used to generate simplest one-instruction addressing for TLS LE model when tls size is smaller 4K. Linker need to make sure there is no TLS offset overflow. 2015-06-01 Jiong Wang <jiong.wang@arm.com> bfd/ * elfnn-aarch64.c (elfNN_aarch64_howto_table): Set overflow type to complain_overflow_unsigned for BFD_RELOC_AARCH64_TLSLE_ADD_LO12. * elfxx-aarch64.c (_bfd_aarch64_elf_resolve_relocation): Don't use PGOFF for BFD_RELOC_AARCH64_TLSLE_ADD_LO12, that will mask off all potential high overflowed bits. ld/testsuite/ * ld-aarch64/tprel_add_lo12_overflow.s: New testcase. * ld-aarch64/tprel_add_lo12_overflow.d: Nex expectation file. * ld-aarch64/aarch64-elf.exp: Run new testcase.
2015-06-01[AArch64] BFD Support BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15Jiong Wang3-0/+24
2015-06-01 Jiong Wang <jiong.wang@arm.com> bfd/ * elfnn-aarch64.c (aarch64_reloc_got_type): Support BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15. (elfNN_aarch64_final_link_relocate): Ditto. (elfNN_aarch64_gc_swap_hook): Ditto. (elfNN_aarch64_check_relocs): Ditto. * elfxx-aarch64.c (_bfd_aarch64_elf_put_addend): Ditto. ld/testsuite/ * ld-aarch64/emit-relocs-313.s: New test file. * ld-aarch64/emit-relocs-313.d: Ditto. * ld-aarch64/aarch64-elf.exp: Run new test.
2015-04-24[AArch64] Improve PC-relative relocation check for shared libraryJiong Wang4-0/+39
2015-04-24 Jiong. Wang <jiong.wang@arm.com> bfd/ * elfnn-aarch64.c (elfNN_aarch64_final_link_relocate): Reject PC-relative relocation for external symbol. ld/testsuite/ * ld-aarch64/pcrel.s: New testcase. * ld-aarch64/pcrel_pic_defiend_local.d: New expect file. * ld-aarch64/pcrel_pic_undefined.d: Ditto. * ld-aarch64/aarch64-elf.exp: Run them.
2015-04-01[AArch64] Workaround for Cortex A53 erratum 843419Marcus Shawcroft3-0/+154
Some early revisions of the Cortex-A53 have an erratum (843419). The details of the erratum are quite complex and involve dynamic conditions. For the purposes of the workaround we have simplified the static conditions to an ADRP in the last two instructions of a 4KByte page, followed within four instructions by a load/store dependent on the ADRP. This patch adds support to conservatively scan for and workaround Cortex A53 erratum 843419. There are two different workaround strategies used. The first is to rewrite ADRP instructions which form part of an erratum sequence with an ADR instruction. In situations where the ADR provides insufficient offset the dependent load or store instruction from the sequence is moved to a stub section and branches are inserted from the original sequence to the relocated instruction and back again. Stub section sizes are rounded up to a multiple of 4096 in order to ensure that the act of inserting work around stubs does not create more errata sequences. Workaround stubs are always inserted into the stub section associated with the input section containing the erratum sequence. This ensures that the fully relocated form of the veneered load store instruction is available at the point in time when the stub section is written.
2015-03-26[AArch64] Fix branch stubs for BETejas Belagod1-0/+74
2015-03-26 Tejas Belagod <tejas.belagod@arm.com> ld/testsuite * ld-aarch64/farcall-back-be.d: New. bfd/ * elfnn-aarch64.c (aarch64_build_one_stub): Replace the call to generic _bfd_final_link_relocate with aarch64_relocate.
2015-03-25[AArch64] Implement branch over stub section.Marcus Shawcroft4-47/+51
Ensure that injection of a stub section does not break a link where there is an xpectation that flow of control can pass from one input section to another simply by linking the input sections in series. The solution here is to allow stub sections to be inserted after any input section (existing behaviour), but inject an additional branch at the start of each stub section such that control flow falling into the stub section will branch over the stub section.
2015-03-25[AArch64] Remove padding before stub sections.Marcus Shawcroft1-1/+0
Lower stub alignment from 8 to 4 bytes thus removing padding between input section content and stub section content.
2015-03-04Allow MOVK for R_AARCH64_TLSLE_MOVW_TPREL_G{0,1}NCRichard Sandiford3-0/+172
bfd/ PR gas/17843 * elfxx-aarch64.c (_bfd_aarch64_elf_put_addend): Expect R_AARCH64_TLSLE_MOVW_TPREL_G0_NC and R_AARCH64_TLSLE_MOVW_TPREL_G1_NC to be used with MOVK rather than MOVZ. gas/ PR gas/17843 * config/tc-aarch64.c (process_movw_reloc_info): Allow R_AARCH64_TLSLE_MOVW_TPREL_G0_NC and R_AARCH64_TLSLE_MOVW_TPREL_G1_NC for MOVK. gas/testsuite/ PR gas/17843 * gas/aarch64/tls.s, gas/aarch64/tls.d: Add test for R_AARCH64_TLSLE_MOVW_TPREL_G0/R_AARCH64_TLSLE_MOVW_TPREL_G1_NC sequence. ld/testsuite/ PR gas/17843 * ld-aarch64/tlsle.s, ld-aarch64/tlsle.d: New test. * ld-aarch64/aarch64-elf.exp: Run it.
2015-02-26[AArch64] Add tiny DESC test cases.Marcus Shawcroft7-0/+92
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