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2020-06-12RISC-V: Drop the privileged spec v1.9 support.Nelson Chu3-219/+225
There is a conflict between v1.9 and v1.9.1 - CSR MISA address. MISA is 0xf10 in v1.9, but change to 0x301 in v1.9.1. The change made MISA writable, but may also cause risk of compatibility. Binutils already support the -mpriv-spec options and ELF priv attributes, which can used to choose what privileged spec you want, and then give a correponding CSR name and address to use. But Gdb and other tools don't have the simialr mechanism for now. However, there are two things can be confirmed, 1. If we don't have a way to control the priv specs, then the changes, like MISA, will cause risk and hard to maintain. 2. We get the guarantee that the CSR address won't be reused in the future specs, even if it is dropped. I'm not sure if Gdb needs to care about the priv spec versions, it is still discussing. But drop the priv spec v1.9, and make sure that we won't reuse the CSR address is a useful solution for now. Also, we might drop the v1.9.1 in a year or two. After that, specs above v1.10 should be compatible anyway. gas/ * testsuite/gas/riscv/priv-reg-fail-version-1p9.d: Removed. * testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Likewise. * testsuite/gas/riscv/priv-reg-version-1p9.d: Likewise. include/ * opcode/riscv-opc.h: Update the defined versions of CSR from PRIV_SPEC_CLASS_1P9 to PRIV_SPEC_CLASS_1P9P1. Also, drop the MISA DECLARE_CSR_ALIAS since it's aborted version is v1.9. * opcode/riscv.h (enum riscv_priv_spec_class): Remove PRIV_SPEC_CLASS_1P9. opcodes/ * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
2020-06-11[PATCH]: aarch64: Refactor representation of system registersAlex Coplan2-0/+9
Prior to this patch, the information describing the AArch64 system registers was separate from the information describing which system registers are available depending on the CPU feature set. Indeed, the latter was implemented as a separate function from the main table with the system register information. This patch remedies this situation and puts the feature information into the system register table itself. This has several advantages: * Having all the information described in one place is easier to maintain. * The logic to check whether a system register is supported now becomes trivial (and much more efficient). Since this patch ended up touching every line of the system register table, I took the opportunity to make the formatting more consistent and remove some redundant comments. Note that there is still more refactoring that could be done along the same lines here (e.g. with the TLB instructions) but this seemed like a reasonable first pass. Testing: * Regression tested an x64 -> aarch64-none-elf cross binutils. * Built aarch64-none-elf cross toolchain, checked newlib startup code still works. * Bootstrapped binutils on aarch64-linux-gnu, regression tested. * Built aarch64 kernel using new binutils with allyesconfig. OK for master? If so, I'll need a maintainer to commit on my behalf since I don't have write access. Thanks, Alex --- include/ChangeLog: 2020-06-11 Alex Coplan <alex.coplan@arm.com> * opcode/aarch64.h (aarch64_sys_reg): Add required features to struct describing system registers. opcodes/ChangeLog: 2020-06-11 Alex Coplan <alex.coplan@arm.com> * aarch64-opc.c (SYSREG): New macro for describing system registers. (SR_CORE): Likewise. (SR_FEAT): Likewise. (SR_RNG): Likewise. (SR_V8_1): Likewise. (SR_V8_2): Likewise. (SR_V8_3): Likewise. (SR_V8_4): Likewise. (SR_PAN): Likewise. (SR_RAS): Likewise. (SR_SSBS): Likewise. (SR_SVE): Likewise. (SR_ID_PFR2): Likewise. (SR_PROFILE): Likewise. (SR_MEMTAG): Likewise. (SR_SCXTNUM): Likewise. (aarch64_sys_regs): Refactor to store feature information in the table. (aarch64_sys_reg_supported_p): Collapse logic for system registers that now describe their own features. (aarch64_pstatefield_supported_p): Likewise.
2020-06-11asan: readelf: process_mips_specific buffer overflowAlan Modra2-9/+14
DT_MIPS_OPTIONS is not a regular array as assumed by readelf. This patch corrects that assumption, and to do so easily, makes various internal (host byte order) structs the same size as external (target byte order) structs. include/ * elf/mips.h (Elf32_RegInfo): Use fixed width integer types. (Elf64_Internal_RegInfo, Elf_Internal_Options): Likewise. binutils/ * readelf.c (process_mips_specific): Assert size of internal types match size of external types, and simplify allocation of internal buffer. Catch possible integer overflow when sanity checking option size. Don't assume options are a regular array. Sanity check reginfo option against option size. Use PRI macros when printing.
2020-06-06Rename PowerPC64 pcrel GOT TLS relocationsAlan Modra2-5/+13
These relocations should have had REL in their names, to reflect the fact that they are pc-relative. Fix that now by adding _PCREL. I've added some back-compatibility code to support anyone using .reloc with the old relocations. include/ * elf/ppc64.h (elf_ppc64_reloc_type): Rename R_PPC64_GOT_TLSGD34 to R_PPC64_GOT_TLSGD_PCREL34, R_PPC64_GOT_TLSLD34 to R_PPC64_GOT_TLSLD_PCREL34, R_PPC64_GOT_TPREL34 to R_PPC64_GOT_TPREL_PCREL34, and R_PPC64_GOT_DTPREL34 to R_PPC64_GOT_DTPREL_PCREL34. bfd/ * reloc.c: Rename BFD_RELOC_PPC64_GOT_TLSGD34 to BFD_RELOC_PPC64_GOT_TLSGD_PCREL34, BFD_RELOC_PPC64_GOT_TLSLD34 to BFD_RELOC_PPC64_GOT_TLSLD_PCREL34, BFD_RELOC_PPC64_GOT_TPREL34 to BFD_RELOC_PPC64_GOT_TPREL_PCREL34, BFD_RELOC_PPC64_GOT_DTPREL34 to BFD_RELOC_PPC64_GOT_DTPREL_PCREL34. * elf64-ppc.c: Update throughout for reloc renaming. (ppc64_elf_reloc_name_lookup): Handle old reloc names. * libbfd.h: Regenerate. * bfd-in2.h: Regenerate. gas/ * config/tc-ppc.c: Update throughout for reloc renaming. elfcpp/ * powerpc.h: Rename R_PPC64_GOT_TLSGD34 to R_PPC64_GOT_TLSGD_PCREL34, R_PPC64_GOT_TLSLD34 to R_PPC64_GOT_TLSLD_PCREL34, R_PPC64_GOT_TPREL34 to R_PPC64_GOT_TPREL_PCREL34, and R_PPC64_GOT_DTPREL34 to R_PPC64_GOT_DTPREL_PCREL34. gold/ * powerpc.cc: Update throughout for reloc renaming.
2020-06-04opcodes: discriminate endianness and insn-endianness in CGEN portsJose E. Marchesi2-2/+7
The CGEN support code in opcodes accesses instruction contents using a couple of functions defined in cgen-opc.c: cgen_get_insn_value and cgen_put_insn_value. These functions use the "instruction endianness" in the CPU description to order the read/written bytes. The process of writing an instruction to the object file is: a) cgen_put_insn_value ;; Writes out the opcodes. b) ARCH_cgen_insert_operand insert_normal insert_1 cgen_put_insn_value ;; Writes out the bytes of the ;; operand. Likewise, the process of reading an instruction from the object file is: a) cgen_get_insn_value ;; Reads the opcodes. b) ARCH_cgen_extract_operand extract_normal extract_1 cgen_get_insn_value ;; Reads in the bytes of the ;; operand. As can be seen above, cgen_{get,put}_insn_value are used to both process the instruction opcodes (the constant fields conforming the base instruction) and also the values of the instruction operands, such as immediates. This is problematic for architectures in which the endianness of instructions is different to the endianness of data. An example is BPF, where instructions are always encoded big-endian but the data may be either big or little. This patch changes the cgen_{get,put}_insn_value functions in order to get an extra argument with the endianness to use, and adapts the existin callers to these functions in order to provide cd->endian or cd->insn_endian, whatever appropriate. Callers like extract_1 and insert_1 pass cd->endian (since they are reading/writing operand values) while callers reading/writing the base instruction pass cd->insn_endian instead. A few little adjustments have been needed in some existing CGEN based ports: * The BPF assembler uses cgen_put_insn_value. It has been adapted to pass the new endian argument. * The mep port has code in mep.opc that uses cgen_{get,put}_insn_value. It has been adapted to pass the new endianargument. Ditto for a call in the assembler. Tested with --enable-targets=all. Regested in all supported targets. No regressions. include/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/cgen.h: Get an `endian' argument in both cgen_get_insn_value and cgen_put_insn_value. opcodes/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument. (cgen_put_insn_value): Likewise. (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value. * cgen-dis.in (print_insn): Likewise. * cgen-ibld.in (insert_1): Likewise. (insert_1): Likewise. (insert_insn_normal): Likewise. (extract_1): Likewise. * bpf-dis.c: Regenerate. * bpf-ibld.c: Likewise. * bpf-ibld.c: Likewise. * cgen-dis.in: Likewise. * cgen-ibld.in: Likewise. * cgen-opc.c: Likewise. * epiphany-dis.c: Likewise. * epiphany-ibld.c: Likewise. * fr30-dis.c: Likewise. * fr30-ibld.c: Likewise. * frv-dis.c: Likewise. * frv-ibld.c: Likewise. * ip2k-dis.c: Likewise. * ip2k-ibld.c: Likewise. * iq2000-dis.c: Likewise. * iq2000-ibld.c: Likewise. * lm32-dis.c: Likewise. * lm32-ibld.c: Likewise. * m32c-dis.c: Likewise. * m32c-ibld.c: Likewise. * m32r-dis.c: Likewise. * m32r-ibld.c: Likewise. * mep-dis.c: Likewise. * mep-ibld.c: Likewise. * mt-dis.c: Likewise. * mt-ibld.c: Likewise. * or1k-dis.c: Likewise. * or1k-ibld.c: Likewise. * xc16x-dis.c: Likewise. * xc16x-ibld.c: Likewise. * xstormy16-dis.c: Likewise. * xstormy16-ibld.c: Likewise. gas/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * cgen.c (gas_cgen_finish_insn): Pass the endianness to cgen_put_insn_value. (gas_cgen_md_apply_fix): Likewise. (gas_cgen_md_apply_fix): Likewise. * config/tc-bpf.c (md_apply_fix): Pass data endianness to cgen_put_insn_value. * config/tc-mep.c (mep_check_ivc2_scheduling): Pass endianness to cgen_put_insn_value. cpu/ChangeLog: 2020-06-02 Jose E. Marchesi <jose.marchesi@oracle.com> * mep.opc (print_slot_insn): Pass the insn endianness to cgen_get_insn_value.
2020-06-04opcodes: support insn endianness in cgen_cpu_openJose E. Marchesi2-1/+13
This patch adds support for a new CGEN_OPEN_INSN_ENDIAN argument for @arch@_cgen_cpu_open. This is useful for architectures in which the endianness of the instruction words is not the same than the endianness used for data. An accompanying patch has been sent to the CGEN mailing list that adds support for this argument on the CGEN side [1]. Its been already pre-approved [2], and will be applied simultaneously with this binutils series. [1] https://sourceware.org/pipermail/cgen/2020q2/002733.html [2] https://sourceware.org/pipermail/cgen/2020q2/002737.html include/ChangeLog: 2020-06-04 Jose E. Marchesi <jemarch@gnu.org> * opcode/cgen.h (enum cgen_cpu_open_arg): New value CGEN_CPU_OPEN_INSN_ENDIAN. opcodes/ChangeLog: 2020-06-04 Jose E. Marchesi <jemarch@gnu.org> * cgen-dis.in (cpu_desc_list): New field `insn_endian'. (print_insn_): Handle instruction endian. * bpf-dis.c: Regenerate. * bpf-desc.c: Regenerate. * epiphany-dis.c: Likewise. * epiphany-desc.c: Likewise. * fr30-dis.c: Likewise. * fr30-desc.c: Likewise. * frv-dis.c: Likewise. * frv-desc.c: Likewise. * ip2k-dis.c: Likewise. * ip2k-desc.c: Likewise. * iq2000-dis.c: Likewise. * iq2000-desc.c: Likewise. * lm32-dis.c: Likewise. * lm32-desc.c: Likewise. * m32c-dis.c: Likewise. * m32c-desc.c: Likewise. * m32r-dis.c: Likewise. * m32r-desc.c: Likewise. * mep-dis.c: Likewise. * mep-desc.c: Likewise. * mt-dis.c: Likewise. * mt-desc.c: Likewise. * or1k-dis.c: Likewise. * or1k-desc.c: Likewise. * xc16x-dis.c: Likewise. * xc16x-desc.c: Likewise. * xstormy16-dis.c: Likewise. * xstormy16-desc.c: Likewise. binutils/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * objdump.c (disassemble_data): Set disasm_info.endian_code to disasm_info.endian after the latter is initialized to the endianness reported by BFD.
2020-06-03RISC-V: Fix the error when building RISC-V linux native gdbserver.Nelson Chu2-3/+8
The original report is as follow, https://sourceware.org/pipermail/binutils/2020-June/111383.html Inlcude the bfd.h in the include/opcode/riscv.h may cause gdbserver fail to build. I just want to use the `bfd_boolean` in the opcodes/riscv-opc.c, but I didn't realize this cause the build failed. Fortunately, I can also use the `int` as the function return types just like others in the opcodes/riscv-opc.c. include/ * opcode/riscv.h: Remove #include "bfd.h". And change the return types of riscv_get_isa_spec_class and riscv_get_priv_spec_class from bfd_boolean to int. opcodes/ * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int. (riscv_get_priv_spec_class): Likewise.
2020-05-28PR26044, Some targets can't be compiled with GCC 10 (tilepro)Alan Modra2-3/+7
Since this value is used in fields of type tilepro_pipeline (as NO_PIPELINE, see tc-tilepro.c) it is appropriate to put it in the tilepro_pipelen enum. This avoids a warning about converting from one enum type to another. PR 26044 * opcode/tilepro.h (TILEPRO_NUM_PIPELINE_ENCODINGS): Move to tilepro_pipeline enum.
2020-05-27ld: Add --warn-textrel and obsolete --warn-shared-textrelH.J. Lu2-5/+22
--warn-shared-textrel and -z text apply to both shared object and PIE. Add --warn-textrel and obsolete --warn-shared-textrel. Consolidate --warn-textrel and -z text/notext/textoff implementation. bfd/ PR ld/22909 * elflink.c (bfd_elf_final_link): Use bfd_link_textrel_check. Check bfd_link_dll when issue a DT_TEXTREL warning. * elfxx-x86.c (maybe_set_textrel): Likewise. (_bfd_x86_elf_size_dynamic_sections): Likewise. include/ PR ld/22909 * bfdlink.h (textrel_check_method): New enum. (bfd_link_textrel_check): New. (bfd_link_info): Replace warn_shared_textrel and error_textrel with textrel_check. ld/ PR ld/22909 * NEWS: Mention --warn-textrel. * ld.texi: Update -z text/notext/textoff. Add --warn-textrel. Remove --warn-shared-textrel. * ldlex.h (option_values): Rename OPTION_WARN_SHARED_TEXTREL to OPTION_WARN_TEXTREL. * lexsup.c (ld_options): Add --warn-textrel. Obsolete --warn-shared-textrel. (parse_args): Updated. (elf_shlib_list_options): Check link_info.textrel_check. * emultempl/elf.em: Updated. * testsuite/ld-elf/pr19539.d: Replace -z notext with --warn-textrel. Expect a warning. * testsuite/ld-i386/warn1.d: Update expected warning.
2020-05-25ELF: Updated comments for ET_EXEC and ET_DYNH.J. Lu2-2/+7
include/elf/common.h has #define ET_EXEC 2 /* Executable file */ #define ET_DYN 3 /* Shared object file */ These predate PIE: https://groups.google.com/forum/#!topic/generic-abi/mBKlSNldFW4 Updated comments to #define ET_EXEC 2 /* Position-dependent executable file */ #define ET_DYN 3 /* Position-independent executable or shared object file */ * elf/common.h: Update comments for ET_EXEC and ET_DYN.
2020-05-20[PATCH v2 0/9] RISC-V: Support version controling for ISA standard ↵Nelson Chu3-261/+344
extensions and CSR 1. Remove the -mriscv-isa-version and --with-riscv-isa-version options. We can still use -march to choose the version for each extensions, so there is no need to add these. 2. Change the arguments of options from [1p9|1p9p1|...] to [1.9|1.9.1|...]. Unlike the architecture string has specified by spec, ther is no need to do the same thing for options. 3. Spilt the patches to reduce the burdens of review. [PATCH 3/7] RISC-V: Support new GAS options and configure options to set ISA versions to [PATCH v2 3/9] RISC-V: Support GAS option -misa-spec to set ISA versions [PATCH v2 4/9] RISC-V: Support configure options to set ISA versions by default. [PATCH 4/7] RISC-V: Support version checking for CSR according to privilege version. to [PATCH v2 5/9] RISC-V: Support version checking for CSR according to privilege spec version. [PATCH v2 6/9] RISC-V: Support configure option to choose the privilege spec version. 4. Use enum class rather than string to compare the choosen ISA spec in opcodes/riscv-opc.c. The behavior is same as comparing the choosen privilege spec. include * opcode/riscv.h: Include "bfd.h" to support bfd_boolean. (enum riscv_isa_spec_class): New enum class. All supported ISA spec belong to one of the class (struct riscv_ext_version): New structure holds version information for the specific ISA. * opcode/riscv-opc.h (DECLARE_CSR): There are two version information, define_version and abort_version. The define_version means which privilege spec is started to define the CSR, and the abort_version means which privilege spec is started to abort the CSR. If the CSR is valid for the newest spec, then the abort_version should be PRIV_SPEC_CLASS_DRAFT. (DECLARE_CSR_ALIAS): Same as DECLARE_CSR, but only for the obselete CSR. * opcode/riscv.h (enum riscv_priv_spec_class): New enum class. Define the current supported privilege spec versions. (struct riscv_csr_extra): Add new fields to store more information about the CSR. We use these information to find the suitable CSR address when user choosing a specific privilege spec. binutils * dwarf.c: Updated since DECLARE_CSR is changed. opcodes * riscv-opc.c (riscv_ext_version_table): The table used to store all information about the supported spec and the corresponding ISA versions. Currently, only Zicsr is supported to verify the correctness of Z sub extension settings. Others will be supported in the future patches. (struct isa_spec_t, isa_specs): List for all supported ISA spec classes and the corresponding strings. (riscv_get_isa_spec_class): New function. Get the corresponding ISA spec class by giving a ISA spec string. * riscv-opc.c (struct priv_spec_t): New structure. (struct priv_spec_t priv_specs): List for all supported privilege spec classes and the corresponding strings. (riscv_get_priv_spec_class): New function. Get the corresponding privilege spec class by giving a spec string. (riscv_get_priv_spec_name): New function. Get the corresponding privilege spec string by giving a CSR version class. * riscv-dis.c: Updated since DECLARE_CSR is changed. * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR according to the chosen version. Build a hash table riscv_csr_hash to store the valid CSR for the chosen pirv verison. Dump the direct CSR address rather than it's name if it is invalid. (parse_riscv_dis_option_without_args): New function. Parse the options without arguments. (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to parse the options without arguments first, and then handle the options with arguments. Add the new option -Mpriv-spec, which has argument. * riscv-dis.c (print_riscv_disassembler_options): Add description about the new OBJDUMP option. ld * testsuite/ld-riscv-elf/attr-merge-arch-01.d: Updated priv attributes according to the -mpriv-spec option. * testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise. bfd * elfxx-riscv.h (riscv_parse_subset_t): Add new callback function get_default_version. It is used to find the default version for the specific extension. * elfxx-riscv.c (riscv_parsing_subset_version): Remove the parameters default_major_version and default_minor_version. Add new bfd_boolean parameter *use_default_version. Set it to TRUE if we need to call the callback rps->get_default_version to find the default version. (riscv_parse_std_ext): Call rps->get_default_version if we fail to find the default version in riscv_parsing_subset_version, and then call riscv_add_subset to add the subset into subset list. (riscv_parse_prefixed_ext): Likewise. (riscv_std_z_ext_strtab): Support Zicsr extensions. * elfnn-riscv.c (riscv_merge_std_ext): Use strcasecmp to compare the strings rather than characters. riscv_merge_arch_attr_info): The callback function get_default_version is only needed for assembler, so set it to NULL int the linker. * elfxx-riscv.c (riscv_estimate_digit): Remove the static. * elfxx-riscv.h: Updated. gas * testsuite/gas/riscv/priv-reg-fail-read-only-01.s: Updated. * config/tc-riscv.c (default_arch_with_ext, default_isa_spec): Static variables which are used to set the ISA extensions. You can use -march (or ELF build attributes) and -misa-spec to set them, respectively. (ext_version_hash): The hash table used to handle the extensions with versions. (init_ext_version_hash): Initialize the ext_version_hash according to riscv_ext_version_table. (riscv_get_default_ext_version): The callback function of riscv_parse_subset_t. According to the choosed ISA spec, get the default version for the specific extension. (riscv_set_arch): Set the callback function. (enum options, struct option md_longopts): Add new option -misa-spec. (md_parse_option): Do not call riscv_set_arch for -march. We will call it later in riscv_after_parse_args. Call riscv_get_isa_spec_class to set default_isa_spec class. (riscv_after_parse_args): Call init_ext_version_hash to initialize the ext_version_hash, and then call riscv_set_arch to set the architecture with versions according to default_arch_with_ext. * testsuite/gas/riscv/attribute-02.d: Set 0p0 as default version for x extensions. * testsuite/gas/riscv/attribute-03.d: Likewise. * testsuite/gas/riscv/attribute-09.d: New testcase. For i-ext, we already set it's version to 2p1 by march, so no need to use the default 2p2 version. For m-ext, we do not set the version by -march and ELF arch attribute, so set the default 2p0 to it. For zicsr, it is not defined in ISA spec 2p2, so set 0p0 to it. * testsuite/gas/riscv/attribute-10.d: New testcase. The version of zicsr is 2p0 according to ISA spec 20191213. * config/tc-riscv.c (DEFAULT_RISCV_ARCH_WITH_EXT) (DEFAULT_RISCV_ISA_SPEC): Default configure option settings. You can set them by configure options --with-arch and --with-isa-spec, respectively. (riscv_set_default_isa_spec): New function used to set the default ISA spec. (md_parse_option): Call riscv_set_default_isa_spec rather than call riscv_get_isa_spec_class directly. (riscv_after_parse_args): If the -isa-spec is not set, then we set the default ISA spec according to DEFAULT_RISCV_ISA_SPEC by calling riscv_set_default_isa_spec. * testsuite/gas/riscv/attribute-01.d: Add -misa-spec=2.2, since the --with-isa-spec may be set to different ISA spec. * testsuite/gas/riscv/attribute-02.d: Likewise. * testsuite/gas/riscv/attribute-03.d: Likewise. * testsuite/gas/riscv/attribute-04.d: Likewise. * testsuite/gas/riscv/attribute-05.d: Likewise. * testsuite/gas/riscv/attribute-06.d: Likewise. * testsuite/gas/riscv/attribute-07.d: Likewise. * configure.ac: Add configure options, --with-arch and --with-isa-spec. * configure: Regenerated. * config.in: Regenerated. * config/tc-riscv.c (default_priv_spec): Static variable which is used to check if the CSR is valid for the chosen privilege spec. You can use -mpriv-spec to set it. (enum reg_class): We now get the CSR address from csr_extra_hash rather than reg_names_hash. Therefore, move RCLASS_CSR behind RCLASS_MAX. (riscv_init_csr_hashes): Only need to initialize one hash table csr_extra_hash. (riscv_csr_class_check): Change the return type to void. Don't check the ISA dependency if -mcsr-check isn't set. (riscv_csr_version_check): New function. Check and find the CSR address from csr_extra_hash, according to default_priv_spec. Report warning for the invalid CSR if -mcsr-check is set. (reg_csr_lookup_internal): Updated. (reg_lookup_internal): Likewise. (md_begin): Updated since DECLARE_CSR and DECLARE_CSR_ALIAS are changed. (enum options, struct option md_longopts): Add new GAS option -mpriv-spec. (md_parse_option): Call riscv_set_default_priv_version to set default_priv_spec. (riscv_after_parse_args): If -mpriv-spec isn't set, then set the default privilege spec to the newest one. (enum riscv_csr_class, struct riscv_csr_extra): Move them to include/opcode/riscv.h. * testsuite/gas/riscv/priv-reg-fail-fext.d: This test case just want to check the ISA dependency for CSR, so fix the spec version by adding -mpriv-spec=1.11. * testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise. There are some version warnings for the test case. * gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise. * gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise. * gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise. * gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise. * gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise. * gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d: New test case. Check whether the CSR is valid when privilege version 1.9 is choosed. * gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Likewise. * gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: New test case. Check whether the CSR is valid when privilege version 1.9.1 is choosed. * gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise. * gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d: New test case. Check whether the CSR is valid when privilege version 1.10 is choosed. * gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise. * gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d: New test case. Check whether the CSR is valid when privilege version 1.11 is choosed. * gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise. * config/tc-riscv.c (DEFAULT_RISCV_ISA_SPEC): Default configure option setting. You can set it by configure option --with-priv-spec. (riscv_set_default_priv_spec): New function used to set the default privilege spec. (md_parse_option): Call riscv_set_default_priv_spec rather than call riscv_get_priv_spec_class directly. (riscv_after_parse_args): If -mpriv-spec isn't set, then we set the default privilege spec according to DEFAULT_RISCV_PRIV_SPEC by calling riscv_set_default_priv_spec. * testsuite/gas/riscv/csr-dw-regnums.d: Add -mpriv-spec=1.11, since the --with-priv-spec may be set to different privilege spec. * testsuite/gas/riscv/priv-reg.d: Likewise. * configure.ac: Add configure option --with-priv-spec. * configure: Regenerated. * config.in: Regenerated. * config/tc-riscv.c (explicit_attr): Rename explicit_arch_attr to explicit_attr. Set it to TRUE if any ELF attribute is found. (riscv_set_default_priv_spec): Try to set the default_priv_spec if the priv attributes are set. (md_assemble): Set the default_priv_spec according to the priv attributes when we start to assemble instruction. (riscv_write_out_attrs): Rename riscv_write_out_arch_attr to riscv_write_out_attrs. Update the arch and priv attributes. If we don't set the corresponding ELF attributes, then try to output the default ones. (riscv_set_public_attributes): If any ELF attribute or -march-attr options is set (explicit_attr is TRUE), then call riscv_write_out_attrs to update the arch and priv attributes. (s_riscv_attribute): Make sure all arch and priv attributes are set before any instruction. * testsuite/gas/riscv/attribute-01.d: Update the priv attributes if any ELF attribute or -march-attr is set. If the priv attributes are not set, then try to update them by the default setting (-mpriv-spec or --with-priv-spec). * testsuite/gas/riscv/attribute-02.d: Likewise. * testsuite/gas/riscv/attribute-03.d: Likewise. * testsuite/gas/riscv/attribute-04.d: Likewise. * testsuite/gas/riscv/attribute-06.d: Likewise. * testsuite/gas/riscv/attribute-07.d: Likewise. * testsuite/gas/riscv/attribute-08.d: Likewise. * testsuite/gas/riscv/attribute-09.d: Likewise. * testsuite/gas/riscv/attribute-10.d: Likewise. * testsuite/gas/riscv/attribute-unknown.d: Likewise. * testsuite/gas/riscv/attribute-05.d: Likewise. Also, the priv spec set by priv attributes must be supported. * testsuite/gas/riscv/attribute-05.s: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p9.d: Likewise. Updated priv attributes according to the -mpriv-spec option. * testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p10.d: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p11.d: Likewise. * testsuite/gas/riscv/priv-reg.d: Removed. * testsuite/gas/riscv/priv-reg-version-1p9.d: New test case. Dump the CSR according to the priv spec 1.9. * testsuite/gas/riscv/priv-reg-version-1p9p1.d: New test case. Dump the CSR according to the priv spec 1.9.1. * testsuite/gas/riscv/priv-reg-version-1p10.d: New test case. Dump the CSR according to the priv spec 1.10. * testsuite/gas/riscv/priv-reg-version-1p11.d: New test case. Dump the CSR according to the priv spec 1.11. * config/tc-riscv.c (md_show_usage): Add descriptions about the new GAS options. * doc/c-riscv.texi: Likewise.
2020-05-19Fix the ARM assembler to generate a Realtime profile for armv8-r.Alexander Fedotov2-1/+7
PR 25992 gas * config/tc-arm.c : Add arm_ext_v8r feature. (it_fsm_post_encode): Check arm_ext_v8r feature. (get_aeabi_cpu_arch_from_fset): Check arm_ext_v8r feature. include * opcode/arm.h (ARM_EXT2_V8R): Define. Modified ARM_AEXT2_V8R.
2020-05-11Power10 Reduced precision outer product operationsAlan Modra2-13/+21
include/ * opcode/ppc.h (PPC_OPERAND_ACC): Define. Renumber following PPC_OPERAND defines. opcodes/ * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a): New functions. (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK, YMSK2, XA6a, XA6ap, XB6a entries. (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define. (PPCVSX4): Define. (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz, xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger, xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp, xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np, xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp, xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn, xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16. (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp, pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8, pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2, pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp, pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp, pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn, pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn. gas/ * config/tc-ppc.c (pre_defined_registers): Add accumulators. (md_assemble): Check acc specified in correct operand. * testsuite/gas/ppc/outerprod.d, * testsuite/gas/ppc/outerprod.s, * testsuite/gas/ppc/vsx4.d, * testsuite/gas/ppc/vsx4.s: New tests. * testsuite/gas/ppc/ppc.exp: Run them.
2020-05-11PowerPC Rename powerxx to power10Alan Modra3-3/+8
Now that ISA3.1 is out we can finish with the powerxx silliness. bfd/ * elf64-ppc.c: Rename powerxx to power10 throughout. gas/ * config/tc-ppc.c (md_assemble): Update for PPC_OPCODE_POWER10 renaming. * testsuite/gas/ppc/prefix-align.d: Use -mpower10/-Mpower10 in place of -mfuture/-Mfuture. * testsuite/gas/ppc/prefix-pcrel.d: Likewise. * testsuite/gas/ppc/prefix-reloc.d: Likewise. gold/ * powerpc.cc: Rename powerxx to power10 throughout. include/ * elf/ppc64.h: Update comment. * opcode/ppc.h (PPC_OPCODE_POWER10): Rename from PPC_OPCODE_POWERXX. ld/ * testsuite/ld-powerpc/callstub-1.d: Use -mpower10/-Mpower10 in place of -mfuture/-Mfuture. * testsuite/ld-powerpc/notoc2.d: Likewise. * testsuite/ld-powerpc/powerpc.exp: Likewise. * testsuite/ld-powerpc/tlsgd.d: Likewise. * testsuite/ld-powerpc/tlsie.d: Likewise. * testsuite/ld-powerpc/tlsld.d: Likewise. opcodes/ * ppc-dis.c (ppc_opts): Add "power10" entry. (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming. * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
2020-04-30AArch64: add GAS support for UDF instructionAlex Coplan2-0/+6
binutils * testsuite/binutils-all/aarch64/in-order-all.d: Update to use new disassembly. * testsuite/binutils-all/aarch64/out-of-order-all.d: Likewise. ld/ * testsuite/ld-aarch64/erratum843419_tls_ie.d: Use udf in disassembly. * testsuite/ld-aarch64/farcall-b-section.d: Likewise. * testsuite/ld-aarch64/farcall-back.d: Likewise. * testsuite/ld-aarch64/farcall-bl-section.d: Likewise. gas/ * config/tc-aarch64.c (fix_insn): Implement for AARCH64_OPND_UNDEFINED. (parse_operands): Implement for AARCH64_OPND_UNDEFINED. * testsuite/gas/aarch64/udf.s: New. * testsuite/gas/aarch64/udf.d: New. * testsuite/gas/aarch64/udf-invalid.s: New. * testsuite/gas/aarch64/udf-invalid.l: New. * testsuite/gas/aarch64/udf-invalid.d: New. include * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_UNDEFINED. opcodes * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2. * aarch64-opc.c (fields): Add entry for FLD_imm16_2. (operand_general_constraint_met_p): validate AARCH64_OPND_UNDEFINED. * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry for FLD_imm16_2. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated.
2020-04-23arc: Add support for ARC HS extra registers in core filesAnton Kolesov2-0/+6
When a coredump is generated, there are a few registers in ARC HS that are put under a special section, namely ".reg-v2". It is for backward compatibility reasons with older tools that we have decided not to extend the generic ".reg" section. This patch makes it possible to display the information better regarding that section. Compare the output of "readelf" without and with these changes: $ readelf -n core # without the patch ... LINUX 0x0000000c Unknown note type: (0x00000600) description data: 78 08 00 00 2f 6c 64 2d 75 43 6c 69 $ readelf -n core # with the patch ... LINUX 0x0000000c NT_ARC_V2 (ARC HS accumulator/extra registers) description data: 78 08 00 00 2f 6c 64 2d 75 43 6c 69 In another commit (soon to be submitted), GDB will makes use of these changes to parse the extra section and its registers. bfd/ChangeLog 2020-03-26 Anton Kolesov <anton.kolesov@synopsys.com> * elf-bfd.h (elfcore_write_arc_v2): Add prototype. * elf.c (elfcore_grok_arc_v2): New function. (elfcore_grok_note): Call the new function to handle the corresponding note. (elfcore_write_arc_v2): New function. (elfcore_write_register_note): Call the new function to handle the corresponding pseudo-sections. binutils/ChangeLog 2020-03-26 Anton Kolesov <anton.kolesov@synopsys.com> * readelf.c (get_note_type): Handle NT_ARC_V2. include/elf/ChangeLog 2020-03-26 Anton Kolesov <anton.kolesov@synopsys.com> * common.h (NT_ARC_V2): New macro definitions.
2020-04-22xtensa: fix PR ld/25861Max Filippov2-0/+12
Introduce new relaxations XTENSA_PDIFF{8,16,32} for positive differences (subtracted symbol precedes diminished symbol) and XTENSA_NDIFF{8,16,32} for negative differences (subtracted symbol follows diminished symbol). Don't generate XTENSA_DIFF relocations in the assembler, generate XTENSA_PDIFF or XTENSA_NDIFF based on relative symbol position. Handle XTENSA_DIFF in BFD for compatibility with old object files. Handle XTENSA_PDIFF and XTENSA_NDIFF in BFD, treating difference value as unsigned. 2020-04-22 Max Filippov <jcmvbkbc@gmail.com> bfd/ * bfd-in2.h: Regenerated. * elf32-xtensa.c (elf_howto_table): New entries for R_XTENSA_PDIFF{8,16,32} and R_XTENSA_NDIFF{8,16,32}. (elf_xtensa_reloc_type_lookup, elf_xtensa_do_reloc) (relax_section): Add cases for R_XTENSA_PDIFF{8,16,32} and R_XTENSA_NDIFF{8,16,32}. * libbfd.h (bfd_reloc_code_real_names): Add names for BFD_RELOC_XTENSA_PDIFF{8,16,32} and BFD_RELOC_XTENSA_NDIFF{8,16,32}. * reloc.c: Add documentation for BFD_RELOC_XTENSA_PDIFF{8,16,32} and BFD_RELOC_XTENSA_NDIFF{8,16,32}. binutils/ * readelf.c (is_none_reloc): Recognize BFD_RELOC_XTENSA_PDIFF{8,16,32} and BFD_RELOC_XTENSA_NDIFF{8,16,32}. gas/ * config/tc-xtensa.c (md_apply_fix): Replace BFD_RELOC_XTENSA_DIFF{8,16,32} generation with BFD_RELOC_XTENSA_PDIFF{8,16,32} and BFD_RELOC_XTENSA_NDIFF{8,16,32} generation. * testsuite/gas/xtensa/loc.d: Replace BFD_RELOC_XTENSA_DIFF16 with BFD_RELOC_XTENSA_PDIFF16 in the expected output. include/ * elf/xtensa.h (elf_xtensa_reloc_type): New entries for R_XTENSA_PDIFF{8,16,32} and R_XTENSA_NDIFF{8,16,32}. ld/ * testsuite/ld-xtensa/relax-loc.d: New test definition. * testsuite/ld-xtensa/relax-loc.s: New test source. * testsuite/ld-xtensa/xtensa.exp (relax-loc): New test.
2020-04-21Remove SH-5 remnantsAlan Modra2-21/+5
git commit 211dc24b87 removed most sh5 and sh64 SuperH support, after they were obsoleted by git commit 2b213129c5. This patch removes a few remaining pieces that should have gone with 211dc24b87. include/ * elf/sh.h (STO_SH5_ISA32, SHF_SH5_ISA32, SHF_SH5_ISA32_MIXED), (SHT_SH5_CR_SORTED, STT_DATALABEL): Delete. bfd/ * elf32-sh.c (sh_elf_relocate_section): Remove STO_SH5_ISA32 processing.
2020-04-15Unify the behaviour of ld.bfd and ld.gold with respect to warning about ↵Fangrui Song2-3/+12
unresolved symbol references. (PR 24613) PR binutils/24613 include * bfdlink.h (enum report_method): Delete RM_GENERATE_WARNING and RM_GENERATE_ERROR. Add RM_DIAGNOSE. (struct bfd_link_info): Add warn_unresolved_syms. ld * lexsup.c (parse_args): Change RM_GENERATE_WARNING and RM_GENERATE_ERROR to RM_DIAGNOSE. * emultempl/aix.em (ld_${EMULATION_NAME}_emulation): Change RM_GENERATE_ERROR to RM_DIAGNOSE. * emultempl/elf.em (ld_${EMULATION_NAME}_emulation): Likewise. bfd * coff-rs6000.c (xcoff_ppc_relocate_section): Change RM_GENERATE_ERROR to RM_DIAGNOSE plus a check of warn_unresolved_syms. * coff64-rs6000.c (xcoff_ppc_relocate_section): Likewise. * elf-bfd.h (_bfd_elf_large_com_section): Likewise. * elf32-m32r.c (m32r_elf_relocate_section): Likewise. * elf32-score.c (s3_bfd_score_elf_relocate_section): Likewise. * elf32-score7.c (s7_bfd_score_elf_relocate_section): Likewise. * elf32-sh.c (sh_elf_relocate_section): Likewise. * elf32-spu.c (spu_elf_relocate_section): Likewise. * elf64-hppa.c (elf64_hppa_relocate_section): Likewise. * elflink.c (elf_link_output_extsym): Likewise. * elfxx-mips.c (mips_elf_calculate_relocation): Likewise.
2020-04-14Fixes for the magic number used in PDP11 AOUT binaries.Stephen Casner2-1/+9
PR ld/25677 include * aout/aout64.h (N_DATADDR): Add IMAGIC case. bfd * pdp11.c: Add implementation of --imagic option. (adjust_o_magic): Fix objcopy --extract-symbol test. * libaout.h (enum aout_magic): Add i_magic. ld * emulparams/pdp11.sh (SCRIPT_NAME): Change to pdp11. (EXTRA_EM_FILE): New, add emulation file pdp11. * scripttempl/pdp11.sc: New, derived from aout.sc without irrelevant input sections. * emultempl/pdp11.em (_add_options, _handle_option) (_list_options): New. Add options -z, --imagic for pdp11-aout. (_before_parse): Make --omagic be default instead of --nmagic. (_get_script): Modify special-case linker script for --imagic. * lexsup.c (parse_args): Explictly set config.text_read_only for -n. * ld.texi (Options): Add documentation of PDP11-specific options. (Options): Fix unrelated typo to --no-compact-branches. * gen-doc.texi: @set PDP11. * testsuite/ld-pdp11/pdp11.exp: New, start pdp11 testing. * testsuite/ld-pdp11/sections.s: New, source for options tests. * testsuite/ld-pdp11/imagic.d: New, test --imagic format. * testsuite/ld-pdp11/imagicz.d: New, test -z (imagic) format. * testsuite/ld-pdp11/nmagic.d: New, test --nmagic format. * testsuite/ld-pdp11/omagic.d: New, test --omagic format.
2020-04-02coff-go32-exe: support variable-length stubsJan W. Jagersma3-48/+7
The stub size in GO32 executables has historically been fixed at 2048 bytes, due to hardcoded limitations in bfd. Recent patches to djgpp by Stas Sergeev (CC'd) have pushed the stub right up to this limit, so if any further expansion is desired, this must first be patched in bfd. This series includes three patches: The first changes the meaning of the bfd->origin field slightly, so that target code can use this to specify an offset into the file where the actual bfd is located. The second patch then uses this to enable support for variable-sized stubs in the coff-go32-exe format. The final patch is only a cleanup, it normalizes function and variable names in coff-stgo32.c so that they all begin with the same prefix. bfd * bfdio.c (bfd_bread, bfd_tell, bfd_seek, bfd_mmap): Always add bfd->origin to file offset. * bfdwin.c (bfd_get_file_window): Likewise. * bfd.c: Clarify the use of the bfd->origin field. * bfd-in2.h: Regenerate. * coff-i386.c: Don't include go32exe.h. Allow overriding coff_write_object_contents via COFF_WRITE_CONTENTS. * coff-stgo32.c (go32exe_cleanup, go32exe_mkobject) (go32exe_write_object_contents): New functions. (go32exe_temp_stub, go32exe_temp_stub_size): New static globals. (COFF_WRITE_CONTENTS, GO32EXE_DEFAULT_STUB_SIZE): Define. (create_go32_stub): Remove check for 2k size limit. Read stub from go32exe_temp_stub if present. (go32_stubbed_coff_bfd_copy_private_bfd_data): Allocate and copy variable-length stub. (go32_check_format): Read stub to go32exe_temp_stub, set origin, return go32exe_cleanup. (adjust_filehdr_in_post, adjust_filehdr_out_pre) (adjust_filehdr_out_post, adjust_scnhdr_in_post) (adjust_scnhdr_out_pre, adjust_scnhdr_out_post) (adjust_aux_in_post, adjust_aux_out_pre, adjust_aux_out_post): Remove functions and their associated #defines. * coffcode.h (coff_mkobject_hook): Remove stub copying code. * libcoff-in.h: (struct coff_tdata): New field stub_size. Rename field go32stub to stub. * libcoff.h: Regenerate. * coff-stgo32.c (go32_check_format): Rename to... (go32exe_check_format): ...this. (go32_stubbed_coff_bfd_copy_private_bfd_data): Rename to... (go32exe_copy_private_bfd_data): ...this. (stub_bytes): Rename to... (go32exe_default_stub): ...this. (create_go32_stub): Rename to... (go32exe_create_stub): ...this. * coff-stgo32.c (go32exe_copy_private_bfd_data): Avoid realloc when possible. include * coff/go32exe.h: Remove file. * coff/internal.h (struct internal_filehdr): Remove field go32stub. Remove flag F_GO32STUB.
2020-04-01include: Sync plugin-api.h with GCCMartin Liska2-1/+7
Fix typo in a macro usage. PR lto/94249 * plugin-api.h: Fix a typo.
2020-03-30RISC-V: Update CSR to privileged spec 1.11.Nelson Chu2-6/+23
gas/ * testsuite/gas/riscv/alias-csr.d: Move this to priv-reg-pseudo. * testsuite/gas/riscv/alias-csr.s: Likewise. * testsuite/gas/riscv/no-aliases-csr.d: Move this to priv-reg-pseudo-noalias. * testsuite/gas/riscv/bad-csr.d: Rename to priv-reg-fail-nonexistent. * testsuite/gas/riscv/bad-csr.l: Likewise. * testsuite/gas/riscv/bad-csr.s: Likewise. * testsuite/gas/riscv/satp.d: Removed. Already included in priv-reg. * testsuite/gas/riscv/satp.s: Likewise. * testsuite/gas/riscv/priv-reg-pseudo.d: New testcase for all pseudo csr instruction, including alias-csr testcase. * testsuite/gas/riscv/priv-reg-pseudo.s: Likewise. * testsuite/gas/riscv/priv-reg-pseudo-noalias.d: New testcase for all pseudo instruction with objdump -Mno-aliases. * testsuite/gas/riscv/priv-reg-fail-nonexistent.d: New testcase. * testsuite/gas/riscv/priv-reg-fail-nonexistent.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-nonexistent.s: Likewise. * testsuite/gas/riscv/priv-reg.d: Update CSR to 1.11. * testsuite/gas/riscv/priv-reg.s: Likewise. * testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise. * testsuite/gas/riscv/csr-dw-regnums.d: Likewise. * testsuite/gas/riscv/csr-dw-regnums.s: Likewise. include/ * opcode/riscv-opc.h: Update CSR to 1.11. gdb/ * features/riscv/32bit-csr.xml: Regenerated. * features/riscv/64bit-csr.xml: Regenerated.
2020-03-26Support AT_BSDFLAGS on FreeBSD.John Baldwin2-0/+5
FreeBSD's kernel recently added a new ELF auxiliary vector entry holding a mask of software features provided by the kernel. This change fixes 'info auxv' to report the name and description for this vector entry instead of '???'. include/ChangeLog: * elf/common.h (AT_FREEBSD_BSDFLAGS): Define. gdb/ChangeLog: * fbsd-tdep.c (fbsd_print_auxv_entry): Handle AT_FREEBSD_BSDFLAGS.
2020-03-24include: Sync plugin-api.h with GCCMartin Liska2-2/+68
Improve endianess detection. PR lto/94249 * plugin-api.h: Add more robust endianess detection.
2020-03-21include: Sync lto-symtab.h and plugin-api.h with GCCMartin Liska3-2/+8
Fix comma at end of enumerator list seen with -std=c++98. * plugin-api.h (enum ld_plugin_symbol_type): Remove comma after last value of an enum. * lto-symtab.h (enum gcc_plugin_symbol_type): Likewise.
2020-03-19Include: Sync lto-symtab.h and plugin-api.h with GCCMartin Liska3-2/+56
2020-03-19 Martin Liska <mliska@suse.cz> * lto-symtab.h (enum gcc_plugin_symbol_type): New. (enum gcc_plugin_symbol_section_kind): Likewise. 2020-03-19 Martin Liska <mliska@suse.cz> * plugin-api.h (struct ld_plugin_symbol): Split int def into 4 char fields. (enum ld_plugin_symbol_type): New. (enum ld_plugin_symbol_section_kind): New. (enum ld_plugin_tag): Add LDPT_ADD_SYMBOLS_V2.
2020-03-14Implement NT_NETBSDCORE_LWPSTATUS (NetBSD-Core)Kamil Rytarowski2-1/+6
bfd/ChangeLog: * elf.c (elfcore_grok_netbsd_note): Add support for NT_NETBSDCORE_LWPSTATUS notes. binutils/ChangeLog: * readelf.c (get_netbsd_elfcore_note_type): Add support for NT_NETBSDCORE_LWPSTATUS notes. include/ChangeLog: * elf/common.h (NT_NETBSDCORE_LWPSTATUS): New define.
2020-03-13Register NT_NETBSDCORE_AUXV (NetBSD-Core)Kamil Rytarowski2-0/+5
* elf/common.h (NT_NETBSDCORE_AUXV): New define.
2020-03-13Add support for non-contiguous memory regionsChristophe Lyon2-0/+13
2020-01-06 Christophe Lyon <christophe.lyon@linaro.org> bfd/ * bfd-in2.h: Regenerate. * section.c (asection): Add already_assigned field. (BFD_FAKE_SECTION): Add default initializer for it. * ecoff.c (bfd_debug_section): Initialize already_assigned field. * elf32-arm.c (arm_build_one_stub): Add support for non_contiguous_regions. * elf32-csky.c (csky_build_one_stub): Likewise. * elf32-hppa.c (hppa_build_one_stub): Likewise. * elf32-m68hc11.c (m68hc11_elf_build_one_stub): Likewise. * elf32-m68hc12.c (m68hc12_elf_build_one_stub): Likewise. * elf32-metag.c (metag_build_one_stub): Likewise. * elf32-nios2.c (nios2_build_one_stub): Likewise. * elf64-ppc.c (ppc_build_one_stub): Likewise. (ppc_size_one_stub): Likewise. * elfnn-aarch64.c (aarch64_build_one_stub): Likewise. * elflink.c (elf_link_input_bfd): Likewise. include/ * bfdlink.h (bfd_link_info): Add non_contiguous_regions and non_contiguous_regions_warnings fields. ld/ * ldlang.c (lang_add_section): Add support for non_contiguous_regions. (size_input_section): Likewise. (lang_size_sections_1): Likewise. (process_insert_statements): Likewise. * ldlex.h (option_values): Add OPTION_NON_CONTIGUOUS_REGIONS and OPTION_NON_CONTIGUOUS_REGIONS_WARNINGS. * lexsup.c (ld_options): Add entries for --enable-non-contiguous-regions and --enable-non-contiguous-regions-warnings. (parse_args): Handle it. * NEWS: Add --enable-non-contiguous-regions and --enable-non-contiguous-regions-warnings. * ld.texi: Add --enable-non-contiguous-regions and --enable-non-contiguous-regions-warnings documentation. * emultempl/armelf.em (elf32_arm_add_stub_section): Add SEC_LINKER_CREATED flag. * emultempl/xtensaelf.em (ld_build_required_section_dependence): Emit an error when --enable-non-contiguous-regions is used. * testsuite/ld-elf/non-contiguous.d: New. * testsuite/ld-elf/non-contiguous.ld: New. * testsuite/ld-elf/non-contiguous.s: New. * testsuite/ld-arm/arm-elf.exp: Run the new tests. * testsuite/ld-arm/arm-elf/non-contiguous-arm.s: New. * testsuite/ld-arm/arm-elf/non-contiguous-arm.d: New. * testsuite/ld-arm/arm-elf/non-contiguous-arm.ld: New. * testsuite/ld-arm/arm-elf/non-contiguous-arm2.d: New. * testsuite/ld-arm/arm-elf/non-contiguous-arm3.ld: New. * testsuite/ld-arm/arm-elf/non-contiguous-arm3.d: New. * testsuite/ld-arm/arm-elf/non-contiguous-arm3.ld: New. * testsuite/ld-arm/arm-elf/non-contiguous-arm4.d: New. * testsuite/ld-arm/arm-elf/non-contiguous-arm4.ld: New. * testsuite/ld-arm/arm-elf/non-contiguous-arm5.d: New. * testsuite/ld-arm/arm-elf/non-contiguous-arm5.ld: New. * testsuite/ld-arm/arm-elf/non-contiguous-arm6.d: New. * testsuite/ld-arm/arm-elf/non-contiguous-arm6.ld: New. * testsuite/ld-powerpc/powerpc.exp: Run new tests. * testsuite/ld-powerpc/non-contiguous-powerpc.d: New. * testsuite/ld-powerpc/non-contiguous-powerpc.ld: New. * testsuite/ld-powerpc/non-contiguous-powerpc.sd: New. * testsuite/ld-powerpc/non-contiguous-powerpc64.d: New.
2020-03-13Fix several mix up between octets and bytes in ELF program headersChristian Eggers3-5/+15
Fixes additional locations not handled in the first patch. When converting between addresses in ELF headers [octets] and bfd LMA/VMA [bytes], the number of octets per byte needs to be incorporated. include/ * bfdlink.h (struct bfd_link_order): Add unit (bytes/octets) to offset and size members. * elf/internal.h (struct elf_internal_phdr): Likewise for p_align member. (struct elf_segment_map): Likewise for p_paddr and p_size members bfd/ * bfd.c (bfd_record_phdr): New local "opb". Fix assignment of "p_paddr" from "at". * elfcode.h (bfd_from_remote_memory): Add units to several parameters. New local "opb". Fix usage of p_align. Fix calculation of "localbase" from "ehdr_vma" and "p_vaddr". Fix call of target_read_memory. * elflink.c (elf_fixup_link_order): Fix scope of "s" local. Fix calculation of "offset" and "output_offset". (bfd_elf_final_link): New local "opb". Fix calculation of "size" from "offset" and fix calculation of "end" from "vma+size". Fix comparison between "sh_addr" and "vma"/"output_offset". (bfd_elf_discard_info): Fix calculation of "eh_alignment". * elf-bfd.h (struct elf_link_hash_table): Add unit to tls_size member. * elf.c (_bfd_elf_map_sections_to_segments): Add unit (bytes/ octets) to "wrap_to2 and "phdr_size" locals. Fix calculation of "wrap_to" value. Add unit (bytes) to phdr_lma variable. Fix assignment of p_paddr from phdr_lma. Fix comparison between "lma+size" and "next->lma". (elf_sort_segments): Fix assignment from p_paddr to lma. (assign_file_positions_for_load_sections): Add unit (bytes) to local "align". Fix calculation of local "off_adjust". Fix calculation of local "filehdr_vaddr". (assign_file_positions_for_non_load_sections): New local "opb". Fix calculation of "end" from "p_size". Fix comparison between "vma+SECTION_SIZE" and "start". Fix calculation of "p_memsz" from "end" and "p_vaddr". (rewrite_elf_program_header): Fix comparison between p_vaddr and vma. Fix assignment to p_paddr from lma. Fix comparison between p_paddr and lma. Fix assignment to p_paddr from lma. * merge.c (sec_merge_emit): New local "opb". Convert "alignment_power" to octets. (_bfd_add_merge_section): New locals "alignment_power" and "opb". Fix comparison between "alignment_power" and "sizeof(align)". (_bfd_merge_sections): New local "opb". Divide size by opb before checking align mask.
2020-03-13Fix several mix up between octets and bytes in ELF program headersChristian Eggers2-12/+19
When converting between addresses in ELF headers [octets] and bfd LMA/VMA [bytes], the number of octets per byte needs to be incorporated. In ld, the SIZEOF_HEADERS linker script statement must be resolved to bytes instead of octets. include/ * elf/internal.h (struct elf_internal_phdr): Add unit (octets) to several member field comments. (Elf_Internal_Shdr): likewise. bfd/ * elf.c (_bfd_elf_make_section_from_shdr): Introduce new temp opb. Divide Elf_Internal_Shdr::sh_addr by opb when setting section LMA/VMA. (_bfd_elf_make_section_from_phdr): Similarly. (elf_fake_sections): Fix calculation of Elf_Internal_shdr::sh_addr from section VMA. (_bfd_elf_map_sections_to_segments): Fix mixup between octets and bytes. (assign_file_positions_for_load_sections): Fix calculations of Elf_Internal_shdr::p_vaddr and p_paddr from section LMA/VMA. Fix comparison between program header address and section LMA. (assign_file_positions_for_non_load_sections): Likewise. (rewrite_elf_program_header): Likewise. Introduce new temp opb. (IS_CONTAINED_BY_VMA): Add parameter opb. (IS_CONTAINED_BY_LMA,IS_SECTION_IN_INPUT_SEGMENT, INCLUDE_SECTION_IN_SEGMENT): Likewise. (copy_elf_program_header): Update call to ELF_SECTION_IN_SEGMENT. Fix calculations of p_addr_valid and p_vaddr_offset. * elflink.c (elf_link_add_object_symbols): Multiply section VMA with octets per byte when comparing against p_vaddr. ld/ * ldexp.c (fold_name): Return SIZEOF_HEADERS in bytes.
2020-03-10ubsan: som: left shift of 1 by 31 placesAlan Modra3-5/+11
* som/aout.h (SOM_AUX_ID_MANDATORY, SOM_SPACE_IS_LOADABLE), (SOM_SYMBOL_HIDDEN, SOM_SYMBOL_HAS_LONG_RETURN): Use 1u << 31. * som/lst.h (LST_SYMBOL_HIDDEN): Likewise.
2020-03-03Add missing AT tags to the ELF common header.Luis Machado2-0/+22
* elf/common.h (AT_L1I_CACHESIZE, AT_L1I_CACHEGEOMETRY) (AT_L1D_CACHESIZE, AT_L1D_CACHEGEOMETRY, AT_L2_CACHESIZE) (AT_L2_CACHEGEOMETRY, AT_L3_CACHESIZE, AT_L3_CACHEGEOMETRY) (AT_MINSIGSTKSZ): New defines, imported from glibc.
2020-02-25Merge upstream GCC changes for include/ and libiberty/ directoriesAndrew Burgess2-2/+10
This commit pulls in the latest changes for the include/ and libiberty/ directories. The last sync was in commit 533da48302a26885a972e4379eccc26b364e5b53. This commit also removes the file libiberty/rust-demangle.h, this file has been removed in upstream GCC, and should have been deleted as part of the previous sync up, which included this ChangeLog entry: 2019-11-16 Eduard-Mihai Burtescu <eddyb@lyken.rs> .... * rust-demangle.h: Remove. I've grep'd over the binutils-gdb source and can find no reference to the rust-demangle.h file, and everything seems to build fine without it, so I assume its continued existence was a mistake. include/ChangeLog: Import from gcc mainline: 2020-02-05 Andrew Burgess <andrew.burgess@embecosm.com> * hashtab.h (htab_remove_elt): Make a parameter const. (htab_remove_elt_with_hash): Likewise. libiberty/ChangeLog: * rust-demangle.h: Removed. Import from gcc mainline: 2020-02-05 Andrew Burgess <andrew.burgess@embecosm.com> * hashtab.c (htab_remove_elt): Make a parameter const. (htab_remove_elt_with_hash): Likewise. 2020-01-23 Alexandre Oliva <oliva@adacore.com> * argv.c (writeargv): Output empty args as "". 2020-01-18 Iain Sandoe <iain@sandoe.co.uk> * cp-demangle.c (cplus_demangle_operators): Add the co_await operator. * testsuite/demangle-expected: Test co_await operator mangling.
2020-02-20RISC-V: Support the ISA-dependent CSR checking.Nelson Chu2-244/+249
According to the riscv privilege spec, some CSR are only valid when rv32 or the specific extension is set. We extend the DECLARE_CSR and DECLARE_CSR_ALIAS to record more informaton we need, and then check whether the CSR is valid according to these information. We report warning message when the CSR is invalid, so we have a choice between error and warning by --fatal-warnings option. Also, a --no-warn/-W option is used to turn the warnings off, if people don't want the warnings. gas/ * config/tc-riscv.c (enum riscv_csr_class): New enum. Used to decide whether or not this CSR is legal in the current ISA string. (struct riscv_csr_extra): New structure to hold all extra information of CSR. (riscv_init_csr_hash): New function. According to the DECLARE_CSR and DECLARE_CSR_ALIAS, insert CSR extra information into csr_extra_hash. Call hash_reg_name to insert CSR address into reg_names_hash. (md_begin): Call riscv_init_csr_hashes for each DECLARE_CSR. (reg_csr_lookup_internal, riscv_csr_class_check): New functions. Decide whether the CSR is valid according to the csr_extra_hash. (init_opcode_hash): Update 'if (hash_error != NULL)' as hash_error is not a boolean. This is same as riscv_init_csr_hash, so keep the consistent usage. * testsuite/gas/riscv/csr-dw-regnums.d: Add -march=rv32if option. * testsuite/gas/riscv/priv-reg.d: Add f-ext by -march option. * testsuite/gas/riscv/priv-reg-fail-fext.d: New testcase. The source file is `priv-reg.s`, and the ISA is rv32i without f-ext, so the f-ext CSR are not allowed. * testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-rv32-only.d: New testcase. The source file is `priv-reg.s`, and the ISA is rv64if, so the rv32-only CSR are not allowed. * testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise. include/ * opcode/riscv-opc.h: Extend DECLARE_CSR and DECLARE_CSR_ALIAS to record riscv_csr_class. opcodes/ * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is changed. gdb/ * riscv-tdep.c: Updated since the DECLARE_CSR is changed. * riscv-tdep.h: Likewise. * features/riscv/rebuild-csr-xml.sh: Generate the 64bit-csr.xml without rv32-only CSR. * features/riscv/64bit-csr.xml: Regernated. binutils/ * dwarf.c: Updated since the DECLARE_CSR is changed.
2020-02-10[binutils][arm] arm support for ARMv8.m Custom Datapath ExtensionMatthew Malcomson2-0/+22
This patch is part of a series that adds support for the Armv8.m ARMv8.m Custom Datapath Extension to binutils. This patch introduces the Custom Instructions Class 1/2/3 (Single/ Dual, Accumulator/Non-accumulator varianats) to the arm backend. The following Custom Instructions are added: cx1, cx1a, cx1d, cx1da, cx2, cx2a, cx2d, cx2da, cx3, cx3a, cx3d, cx3da. Specification can be found at https://developer.arm.com/docs/ddi0607/latest This patch distinguishes between enabling CDE for different coprocessor numbers by defining multiple architecture flags. This means that the parsing of the architecture extension flags is kept entirely in the existing code path. We introduce a new IT block state to indicate the behaviour of these instructions. This new state allows being used in an IT block or outside an IT block, but does not allow the instruction to be used inside a VPT block. We need this since the CX*A instruction versions can be used in IT blocks, but they aren't to have the conditional suffixes on them. Hence we need to mark an instruction as allowed in either position. We also need a new flag to objdump, in order to determine whether to disassemble an instruction as CDE related or not. Successfully regression tested on arm-none-eabi, and arm-wince-pe. gas/ChangeLog: 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com> Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-arm.c (arm_ext_cde*): New feature sets for each CDE coprocessor that can be enabled. (enum pred_instruction_type): New pred type. (BAD_NO_VPT): New error message. (BAD_CDE): New error message. (BAD_CDE_COPROC): New error message. (enum operand_parse_code): Add new immediate operands. (parse_operands): Account for new immediate operands. (check_cde_operand): New. (cde_coproc_enabled): New. (cde_coproc_pos): New. (cde_handle_coproc): New. (cxn_handle_predication): New. (do_custom_instruction_1): New. (do_custom_instruction_2): New. (do_custom_instruction_3): New. (do_cx1): New. (do_cx1a): New. (do_cx1d): New. (do_cx1da): New. (do_cx2): New. (do_cx2a): New. (do_cx2d): New. (do_cx2da): New. (do_cx3): New. (do_cx3a): New. (do_cx3d): New. (do_cx3da): New. (handle_pred_state): Define new IT block behaviour. (insns): Add newn CX*{,d}{,a} instructions. (CDE_EXTENSIONS,armv8m_main_ext_table,armv8_1m_main_ext_table): Define new cdecp extension strings. * doc/c-arm.texi: Document new cdecp extension arguments. * testsuite/gas/arm/cde-scalar.d: New test. * testsuite/gas/arm/cde-scalar.s: New test. * testsuite/gas/arm/cde-warnings.d: New test. * testsuite/gas/arm/cde-warnings.l: New test. * testsuite/gas/arm/cde-warnings.s: New test. * testsuite/gas/arm/cde.d: New test. * testsuite/gas/arm/cde.s: New test. include/ChangeLog: 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com> Matthew Malcomson <matthew.malcomson@arm.com> * opcode/arm.h (ARM_EXT2_CDE): New extension macro. (ARM_EXT2_CDE0): New extension macro. (ARM_EXT2_CDE1): New extension macro. (ARM_EXT2_CDE2): New extension macro. (ARM_EXT2_CDE3): New extension macro. (ARM_EXT2_CDE4): New extension macro. (ARM_EXT2_CDE5): New extension macro. (ARM_EXT2_CDE6): New extension macro. (ARM_EXT2_CDE7): New extension macro. opcodes/ChangeLog: 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com> Matthew Malcomson <matthew.malcomson@arm.com> * arm-dis.c (struct cdeopcode32): New. (CDE_OPCODE): New macro. (cde_opcodes): New disassembly table. (regnames): New option to table. (cde_coprocs): New global variable. (print_insn_cde): New (print_insn_thumb32): Use print_insn_cde. (parse_arm_disassembler_options): Parse coprocN args.
2020-02-07Add support for the GBZ80 and Z80N variants of the Z80 architecture, and add ↵Sergey Belyashov3-0/+10
DWARF debug info support to the Z80 assembler. PR 25469 bfd * archures.c: Add GBZ80 and Z80N machine values. * reloc.c: Add BFD_RELOC_Z80_16_BE. * coff-z80.c: Add support for new reloc. * coffcode.h: Add support for new machine values. * cpu-z80.c: Add support for new machine names. * elf32-z80.c: Add support for new reloc. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. binutils* readelf.c (get_machine_flags): Add support for Z80N machine number. gas * config/tc-z80.c: Add -gbz80 command line option to generate code for the GameBoy Z80. Add support for generating DWARF. * config/tc-z80.h: Add support for DWARF debug information generation. * doc/c-z80.texi: Document new command line option. * testsuite/gas/z80/gbz80_all.d: New file. * testsuite/gas/z80/gbz80_all.s: New file. * testsuite/gas/z80/z80.exp: Run the new tests. * testsuite/gas/z80/z80n_all.d: New file. * testsuite/gas/z80/z80n_all.s: New file. * testsuite/gas/z80/z80n_reloc.d: New file. include * coff/internal.h (R_IMM16BE): Define. * elf/z80.h (EF_Z80_MACH_Z80N): Define. (R_Z80_16_BE): New reloc. ld * emulparams/elf32z80.sh: Use z80 emulation. * emultempl/z80.em: Make generic to both COFF and ELF Z80 emulations. * emultempl/z80elf.em: Delete. * testsuite/ld-elf/pr22450.d: Expect to fail for the Z80. * testsuite/ld-elf/sec64k.exp: Fix Z80 assembly. * testsuite/ld-unique/pr21529.s: Avoid register name conflict. * testsuite/ld-unique/unique.s: Likewise. * testsuite/ld-unique/unique_empty.s: Likewise. * testsuite/ld-unique/unique_shared.s: Likewise. * testsuite/ld-unique/unique.d: Updated expected output. * testsuite/ld-z80/arch_z80n.d: New file. * testsuite/ld-z80/comb_arch_z80_z80n.d: New file. * testsuite/ld-z80/labels.s: Add more labels. * testsuite/ld-z80/relocs.s: Add more reloc tests. * testsuite/ld-z80/relocs_f_z80n.d: New file opcodes * z80-dis.c: Add support for GBZ80 opcodes.
2020-02-04ubsan: d30v: negation of -2147483648Alan Modra2-1/+5
include/ * opcode/d30v.h (struct pd_reg): Make value field unsigned. opcodes/ * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2020-01-30Add some new PE_IMAGE_DEBUG_TYPE valuesJon Turney2-0/+11
IMAGE_DEBUG_TYPE_REPRO is defined in the latest version of the PE specification [1]. The others are defined in Windows SDK headers and/or reported by DUMPBIN. [1] https://docs.microsoft.com/en-us/windows/win32/debug/pe-format bfd/ChangeLog: 2020-01-16 Jon Turney <jon.turney@dronecode.org.uk> * peXXigen.c (debug_type_names): Add names for new debug data type values. include/ChangeLog: 2020-01-16 Jon Turney <jon.turney@dronecode.org.uk> * coff/internal.h (PE_IMAGE_DEBUG_TYPE_VC_FEATURE) (PE_IMAGE_DEBUG_TYPE_POGO, PE_IMAGE_DEBUG_TYPE_ILTCG) (PE_IMAGE_DEBUG_TYPE_MPX, PE_IMAGE_DEBUG_TYPE_REPRO): Add.
2020-01-18Add markers for 2.34 branch to the NEWS files and ChangeLogs.Nick Clifton1-0/+4
2020-01-17Update libiberty sources with changes in the gcc mainline.Nick Clifton4-24/+87
+2020-01-01 Jakub Jelinek <jakub@redhat.com> + + Update copyright years. + +2019-12-06 Tim Ruehsen <tim.ruehsen@gmx.de> + + * make-relative-prefix.c (split_directories): + Return early on empty 'name' + +2019-11-16 Tim Ruehsen <tim.ruehsen@gmx.de> + + * cp-demangle.c (d_print_init): Remove const from 4th param. + (cplus_demangle_fill_name): Initialize d->d_counting. + (cplus_demangle_fill_extended_operator): Likewise. + (cplus_demangle_fill_ctor): Likewise. + (cplus_demangle_fill_dtor): Likewise. + (d_make_empty): Likewise. + (d_count_templates_scopes): Remobe const from 3rd param, + Return on dc->d_counting > 1, + Increment dc->d_counting. + * cp-demint.c (cplus_demangle_fill_component): Initialize d->d_counting. + (cplus_demangle_fill_builtin_type): Likewise. + (cplus_demangle_fill_operator): Likewise. + +2019-11-16 Eduard-Mihai Burtescu <eddyb@lyken.rs> + + * cplus-dem.c (cplus_demangle): Use rust_demangle directly. + (rust_demangle): Remove. + * rust-demangle.c (is_prefixed_hash): Rename to is_legacy_prefixed_hash. + (parse_lower_hex_nibble): Rename to decode_lower_hex_nibble. + (parse_legacy_escape): Rename to decode_legacy_escape. + (rust_is_mangled): Remove. + (struct rust_demangler): Add. + (peek): Add. + (next): Add. + (struct rust_mangled_ident): Add. + (parse_ident): Add. + (rust_demangle_sym): Remove. + (print_str): Add. + (PRINT): Add. + (print_ident): Add. + (rust_demangle_callback): Add. + (struct str_buf): Add. + (str_buf_reserve): Add. + (str_buf_append): Add. + (str_buf_demangle_callback): Add. + (rust_demangle): Add. + * rust-demangle.h: Remove. + +2019-11-15 Miguel Saldivar <saldivarcher@gmail.com> + + * testsuite/demangle-expected: Fix test. + +2019-11-04 Kamlesh Kumar <kamleshbhalui@gmail.com> + + * cp-demangle.c (d_expr_primary): Handle + nullptr demangling. + * testsuite/demangle-expected: Added test. + +2019-10-29 Paul Pluzhnikov <ppluzhnikov@google.com> + + * cp-demangle.c (d_number): Avoid signed int overflow. + +2019-10-28 Miguel Saldivar <saldivarcher@gmail.com> + + * cp-demangle.c (d_print_mod): Add a space before printing `complex` + and `imaginary`, as opposed to after. + * testsuite/demangle-expected: Adjust test. + +2019-10-03 Eduard-Mihai Burtescu <eddyb@lyken.rs> + + * rust-demangle.c (looks_like_rust): Remove. + (rust_is_mangled): Don't check escapes. + (is_prefixed_hash): Allow 0-9a-f permutations. + (rust_demangle_sym): Don't bail on unknown escapes. + * testsuite/rust-demangle-expected: Update 'main::$99$' test. + +2019-09-03 Eduard-Mihai Burtescu <eddyb@lyken.rs> + + * rust-demangle.c (unescape): Remove. + (parse_lower_hex_nibble): New function. + (parse_legacy_escape): New function. + (is_prefixed_hash): Use parse_lower_hex_nibble. + (looks_like_rust): Use parse_legacy_escape. + (rust_demangle_sym): Use parse_legacy_escape. + * testsuite/rust-demangle-expected: Add 'llv$u6d$' test. + +2019-08-27 Martin Liska <mliska@suse.cz> + + PR lto/91478 + * simple-object-elf.c (simple_object_elf_copy_lto_debug_sections): + First find a WEAK HIDDEN symbol in symbol table that will be + preserved. Later, use the symbol name for all removed symbols. + +2019-08-12 Martin Liska <mliska@suse.cz> + + * Makefile.in: Add filedescriptor.c. + * filedescriptor.c: New file. + * lrealpath.c (is_valid_fd): Remove. diff --git a/libiberty/Makefile.in b/libiberty/Makefile.in index 0be45b4ae8..fe738d0db4 100644 --- a/libiberty/Makefile.in +++ b/libiberty/Makefile.in @@ -1,7 +1,7 @@ # Makefile for the libiberty library. # Originally written by K. Richard Pixley <rich@cygnus.com>. # -# Copyright (C) 1990-2019 Free Software Foundation, Inc. +# Copyright (C) 1990-2020 Free Software Foundation, Inc. # # This file is part of the libiberty library. # Libiberty is free software; you can redistribute it and/or @@ -127,7 +127,7 @@ CFILES = alloca.c argv.c asprintf.c atexit.c \ calloc.c choose-temp.c clock.c concat.c cp-demangle.c \ cp-demint.c cplus-dem.c crc32.c \ d-demangle.c dwarfnames.c dyn-string.c \ - fdmatch.c ffs.c fibheap.c filename_cmp.c floatformat.c \ + fdmatch.c ffs.c fibheap.c filedescriptor.c filename_cmp.c floatformat.c \ fnmatch.c fopen_unlocked.c \ getcwd.c getopt.c getopt1.c getpagesize.c getpwd.c getruntime.c \ gettimeofday.c \ @@ -171,6 +171,7 @@ REQUIRED_OFILES = \ ./cp-demint.$(objext) ./crc32.$(objext) ./d-demangle.$(objext) \ ./dwarfnames.$(objext) ./dyn-string.$(objext) \ ./fdmatch.$(objext) ./fibheap.$(objext) \ + ./filedescriptor.$(objext) \ ./filename_cmp.$(objext) ./floatformat.$(objext) \ ./fnmatch.$(objext) ./fopen_unlocked.$(objext) \ ./getopt.$(objext) ./getopt1.$(objext) ./getpwd.$(objext) \ @@ -756,6 +757,17 @@ $(CONFIGURED_OFILES): stamp-picdir stamp-noasandir else true; fi $(COMPILE.c) $(srcdir)/fibheap.c $(OUTPUT_OPTION) +./filedescriptor.$(objext): $(srcdir)/filedescriptor.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/filedescriptor.c -o pic/$@; \ + else true; fi + if [ x"$(NOASANFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(NOASANFLAG) $(srcdir)/filedescriptor.c -o noasan/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/filedescriptor.c $(OUTPUT_OPTION) + + ./filename_cmp.$(objext): $(srcdir)/filename_cmp.c config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \ $(INCDIR)/safe-ctype.h diff --git a/libiberty/_doprnt.c b/libiberty/_doprnt.c index d44dc415ed..a739f4304f 100644 --- a/libiberty/_doprnt.c +++ b/libiberty/_doprnt.c @@ -1,5 +1,5 @@ /* Provide a version of _doprnt in terms of fprintf. - Copyright (C) 1998-2019 Free Software Foundation, Inc. + Copyright (C) 1998-2020 Free Software Foundation, Inc. Contributed by Kaveh Ghazi (ghazi@caip.rutgers.edu) 3/29/98 This program is free software; you can redistribute it and/or modify it diff --git a/libiberty/argv.c b/libiberty/argv.c index 6444896f99..8c9794db6a 100644 --- a/libiberty/argv.c +++ b/libiberty/argv.c @@ -1,5 +1,5 @@ /* Create and destroy argument vectors (argv's) - Copyright (C) 1992-2019 Free Software Foundation, Inc. + Copyright (C) 1992-2020 Free Software Foundation, Inc. Written by Fred Fish @ Cygnus Support This file is part of the libiberty library. diff --git a/libiberty/asprintf.c b/libiberty/asprintf.c index 5718682f69..6e38e2234d 100644 --- a/libiberty/asprintf.c +++ b/libiberty/asprintf.c @@ -1,6 +1,6 @@ /* Like sprintf but provides a pointer to malloc'd storage, which must be freed by the caller. - Copyright (C) 1997-2019 Free Software Foundation, Inc. + Copyright (C) 1997-2020 Free Software Foundation, Inc. Contributed by Cygnus Solutions. This file is part of the libiberty library. diff --git a/libiberty/choose-temp.c b/libiberty/choose-temp.c index 72c1b710bd..49a2faaa51 100644 --- a/libiberty/choose-temp.c +++ b/libiberty/choose-temp.c @@ -1,5 +1,5 @@ /* Utility to pick a temporary filename prefix. - Copyright (C) 1996-2019 Free Software Foundation, Inc. + Copyright (C) 1996-2020 Free Software Foundation, Inc. This file is part of the libiberty library. Libiberty is free software; you can redistribute it and/or diff --git a/libiberty/clock.c b/libiberty/clock.c index a3730714bd..0de74657d0 100644 --- a/libiberty/clock.c +++ b/libiberty/clock.c @@ -1,5 +1,5 @@ /* ANSI-compatible clock function. - Copyright (C) 1994-2019 Free Software Foundation, Inc. + Copyright (C) 1994-2020 Free Software Foundation, Inc. This file is part of the libiberty library. This library is free software; you can redistribute it and/or modify it under the diff --git
2020-01-16[binutils][arm] PR25376 Change MVE into a CORE_HIGH featureAndre Vieira2-4/+11
This patch moves MVE feature bits into the CORE_HIGH section. This makes sure .fpu and -mfpu does not reset the bits set by MVE. This is important because .fpu has no option to "set" these same bits and thus, mimic'ing GCC, we choose to define MVE as an architecture extension rather than put it together with other the legacy fpu features. This will enable the following behavior: .arch armv8.1-m.main .arch mve .fpu fpv5-sp-d16 #does not disable mve. vadd.i32 q0, q1, q2 This patch also makes sure MVE is not taken into account during auto-detect. This was already the case, but because we moved the MVE bits to the architecture feature space we must make sure ARM_ANY does not include MVE. gas/ChangeLog: 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com> PR 25376 * config/tc-arm.c (mve_ext, mve_fp_ext): Use CORE_HIGH. (armv8_1m_main_ext_table): Use CORE_HIGH for mve. * testsuite/arm/armv8_1-m-fpu-mve-1.s: New. * testsuite/arm/armv8_1-m-fpu-mve-1.d: New. * testsuite/arm/armv8_1-m-fpu-mve-2.s: New. * testsuite/arm/armv8_1-m-fpu-mve-2.d: New. include/ChangeLog: 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com> PR 25376 * opcodes/arm.h (FPU_MVE, FPU_MVE_FPU): Move these features to... (ARM_EXT2_MVE, ARM_EXT2_MVE_FP): ... the CORE_HIGH space. (ARM_ANY): Redefine to not include any MVE bits. (ARM_FEATURE_ALL): Removed. opcodes/ChangeLog: 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com> PR 25376 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits. (neon_opcodes): Likewise. (select_arm_features): Make sure we enable MVE bits when selecting armv8.1-m.main. Make sure we do not enable MVE bits when not selecting any architecture.
2020-01-15MSP430: Fix relocation overflow when using #lo(EXP) macroJozef Lawrynowicz2-0/+20
gas/ChangeLog: 2020-01-15 Jozef Lawrynowicz <jozef.l@mittosystems.com> * config/tc-msp430.c (CHECK_RELOC_MSP430): Always generate 430X relocations when the target is 430X, except when extracting part of an expression. (msp430_srcoperand): Adjust comment. Initialize the expp member of the msp430_operand_s struct as appropriate. (msp430_dstoperand): Likewise. * testsuite/gas/msp430/msp430.exp: Run new test. * testsuite/gas/msp430/reloc-lo-430x.d: New test. * testsuite/gas/msp430/reloc-lo-430x.s: New test. include/ChangeLog: 2020-01-15 Jozef Lawrynowicz <jozef.l@mittosystems.com> * opcode/msp430.h (enum msp430_expp_e): New. (struct msp430_operand_s): Add expp member to struct. ld/ChangeLog: 2020-01-15 Jozef Lawrynowicz <jozef.l@mittosystems.com> * testsuite/ld-msp430-elf/msp430-elf.exp: Run new test. * testsuite/ld-msp430-elf/reloc-lo-430x.s: New test.
2020-01-13[ARC][committed] Update ARC cpu listClaudiu Zissulescu2-0/+8
include/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * elf/arc-cpu.def: Update ARC cpu list.
2020-01-13tic4x: sign extension using shiftsAlan Modra2-5/+13
Don't do that. Especially don't use shift counts that assume the type being shifted is 32 bits when the type is long/unsigned long. Also reverts part of a change I made on 2019-12-11 to tic4x_print_register that on closer inspection turns out to be unnecessary. include/ * opcode/tic4x.h (EXTR): Delete. (EXTRU, EXTRS, INSERTU, INSERTS): Rewrite without zero/sign extension using shifts. Do trim INSERTU value to specified bitfield. opcodes/ * tic4x-dis.c (tic4x_print_register): Remove dead code. gas/ * config/tc-tic4x.c (tic4x_operands_match): Correct tic3x trap insertion.
2020-01-10ubsan: spu: left shift of negative valueAlan Modra2-17/+29
Also fixes a real bug. The DECODE_INSN_I9a and DECODE_INSN_I9b both use UNSIGNED_EXTRACT for 7 low bits of the result, but this was an unsigned value due to "insn" being unsigned. DECODE_INSN_I9* is therefore unsigned too, leading to a zero extension in an expression using a bfd_vma if bfd_vma is 64 bits. * opcode/spu.h: Formatting. (UNSIGNED_EXTRACT): Use 1u. (SIGNED_EXTRACT): Don't sign extend with shifts. (DECODE_INSN_I9a, DECODE_INSN_I9b): Avoid left shift of signed value. Keep result signed. (DECODE_INSN_U9a, DECODE_INSN_U9b): Delete.
2020-01-07[ARC] Add finer details for LLOCK and SCONDShahab Vahedi2-0/+6
This patch changes the "class" of LLOCK/SCOND from "MEMORY" to "LLOCK/SCOND" respectively. Moreover, it corrects the "data_size_mode". These changes are necessary for GDB's atmoic sequence handler. Signed-off-by: Shahab Vahedi <shahab@synopsys.com>
2020-01-02Add support for the GBZ80, Z180, and eZ80 variants of the Z80 architecure. ↵Sergey Belyashov3-0/+62
Add an ELF based target for these as well. PR 25224 bfd * Makefile.am: Add z80-elf target support. * configure.ac: Likewise. * targets.c: Likewise. * config.bfd: Add z80-elf target support and new arches: ez80 and z180. * elf32-z80.c: New file. * archures.c: Add new z80 architectures: eZ80 and Z180. * coffcode.h: Likewise. * cpu-z80.c: Likewise. * bfd-in2.h: Likewise plus additional Z80 relocations. * coff-z80.c: Add new relocations for Z80 target and local label check. gas * config/tc-z80.c: Add new architectures: Z180 and eZ80. Add support for assembler code generated by SDCC. Add new relocation types. Add z80-elf target support. * config/tc-z80.h: Add z80-elf target support. Enable dollar local labels. Local labels starts from ".L". * testsuite/gas/all/fwdexp.d: Fix failure due to symbol conflict. * testsuite/gas/all/fwdexp.s: Likewise. * testsuite/gas/z80/suffix.d: Fix failure on ELF target. * testsuite/gas/z80/z80.exp: Add new tests * testsuite/gas/z80/dollar.d: New file. * testsuite/gas/z80/dollar.s: New file. * testsuite/gas/z80/ez80_adl_all.d: New file. * testsuite/gas/z80/ez80_adl_all.s: New file. * testsuite/gas/z80/ez80_adl_suf.d: New file. * testsuite/gas/z80/ez80_isuf.s: New file. * testsuite/gas/z80/ez80_z80_all.d: New file. * testsuite/gas/z80/ez80_z80_all.s: New file. * testsuite/gas/z80/ez80_z80_suf.d: New file. * testsuite/gas/z80/r800_extra.d: New file. * testsuite/gas/z80/r800_extra.s: New file. * testsuite/gas/z80/r800_ii8.d: New file. * testsuite/gas/z80/r800_z80_doc.d: New file. * testsuite/gas/z80/z180.d: New file. * testsuite/gas/z80/z180.s: New file. * testsuite/gas/z80/z180_z80_doc.d: New file. * testsuite/gas/z80/z80_doc.d: New file. * testsuite/gas/z80/z80_doc.s: New file. * testsuite/gas/z80/z80_ii8.d: New file. * testsuite/gas/z80/z80_ii8.s: New file. * testsuite/gas/z80/z80_in_f_c.d: New file. * testsuite/gas/z80/z80_in_f_c.s: New file. * testsuite/gas/z80/z80_op_ii_ld.d: New file. * testsuite/gas/z80/z80_op_ii_ld.s: New file. * testsuite/gas/z80/z80_out_c_0.d: New file. * testsuite/gas/z80/z80_out_c_0.s: New file. * testsuite/gas/z80/z80_reloc.d: New file. * testsuite/gas/z80/z80_reloc.s: New file. * testsuite/gas/z80/z80_sli.d: New file. * testsuite/gas/z80/z80_sli.s: New file. ld * Makefile.am: Add new target z80-elf * configure.tgt: Likewise. * emultempl/z80.em: Add support for eZ80 and Z180 architectures. * emulparams/elf32z80.sh: New file. * emultempl/z80elf.em: Likewise. * testsuite/ld-z80/arch_ez80_adl.d: Likewise. * testsuite/ld-z80/arch_ez80_z80.d: Likewise. * testsuite/ld-z80/arch_r800.d: Likewise. * testsuite/ld-z80/arch_z180.d: Likewise. * testsuite/ld-z80/arch_z80.d: Likewise. * testsuite/ld-z80/comb_arch_ez80_z80.d: Likewise. * testsuite/ld-z80/comb_arch_z180.d: Likewise. * testsuite/ld-z80/labels.s: Likewise. * testsuite/ld-z80/relocs.s: Likewise. * testsuite/ld-z80/relocs_b_ez80.d: Likewise. * testsuite/ld-z80/relocs_b_z80.d: Likewise. * testsuite/ld-z80/relocs_f_z80.d: Likewise. * testsuite/ld-z80/z80.exp: Likewise. opcodes * z80-dis.c: Add support for eZ80 and Z80 instructions.
2020-01-02Enable building the s12z target on Solaris hosts where REG_Y is defined in ↵Nick Clifton2-10/+18
system header files. * opcode/s12z.h: Undef REG_Y.
generated by cgit v1.1 at 2024-11-19 22:25:14 +0000